A low-power design method using multiple supply voltages

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A low-power design method using multiple supply voltages

Full text

Pdf (734 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 36 - 41

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Mutsunori Igarashi	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Kimiyoshi Usami	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Kazutaka Nogami	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Fumihiro Minami	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Yukio Kawasaki	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Takahiro Aoki	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Midori Takano	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Chiharo Mizuno	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Takashi Ishikawa	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Masahiro Kanazawa	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Shinji Sonoda	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Makoto Ichida	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Naoyuki Hatanaka	Toshiba Corporation, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 55, Citation Count: 23

Additional Information:

references cited by collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/263272.263279 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Massoud Pedram , Jan M. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, Norwell, MA, 2002
	2	Kimiyoshi Usami , Mark Horowitz, Clustered voltage scaling technique for low-power design, Proceedings of the 1995 international symposium on Low power design, p.3-8, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224083]
	3	K.Usami et al., "Low-power Design technique for ASICs by Partially Reducing Supply Voltage",Proc. IEEE International ASIC Conference, pp.301-304, Sep. 1996.
	4	M.Murakata et al.,"Concurrent Logic and Layout Design System for High Performance LSIs", Proc. IEEE Custom Integrated Circuits Conference, pp.465-468, May 1995.
	5	K.Usami et al., "Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor", Proc. IEEE 1997 Custom Integrated Circuits Conference, pp.131-134, May, 1997.
	6	T. Aoki , M. Murakata , T. Mitsuhashi , N. Goto, Fanout-tree restructuring algorithm for post-placement timing optimization, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.66-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224943]
	7	M.Igarashi et al., "Timing Driven Placement with an RC Wire Delay Model for Sub-Micron CMOS Gate- Arrays",Synthesis and Simulation Meeting and International interchange, pp. 235-244 Oct. 1993.
	8	F.Minami and M.Takano," Clock Tree Synthesis Based on RC Delay Balancing "IEEE Custom Integrated Circuit Conf.,pp.28.3.1-28.3.4, ! 992.

CITED BY 23

	Rob A. Rutenbar , L. Richard Carley , Roberto Zafalon , Nicola Dragone, Low-power technology mapping for mixed-swing logic, Proceedings of the 2001 international symposium on Low power electronics and design, p.291-294, August 2001, Huntington Beach, California, United States
	Bryan Ackland , Chris Nicol, High performance DSPs - what's hot and what's not?, Proceedings of the 1998 international symposium on Low power electronics and design, p.1-6, August 10-12, 1998, Monterey, California, United States
	Kimiyoshi Usami , Mutsunori Igarashi , Takashi Ishikawa , Masahiro Kanazawa , Masafumi Takahashi , Mototsugu Hamada , Hideho Arakida , Toshihiro Terazawa , Tadahiro Kuroda, Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques, Proceedings of the 35th annual conference on Design automation, p.483-488, June 15-19, 1998, San Francisco, California, United States
	Jatuchai Pangjun , Sachin S. Sapatnekar, Clock distribution using multiple voltages, Proceedings of the 1999 international symposium on Low power electronics and design, p.145-150, August 16-17, 1999, San Diego, California, United States
	Seong-Ook Jung , Ki-Wook Kim , Sung-Mo Kang, Low-swing clock domino logic incorporating dual supply and dual threshold voltages, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Kimiyoshi Usami , Mutsunori Igarashi, Low-power design methodology and applications utilizing dual supply voltages, Proceedings of the 2000 conference on Asia South Pacific design automation, p.123-128, January 2000, Yokohama, Japan
	Vijay Sundararajan , Keshab K. Parhi, Synthesis of low power CMOS VLSI circuits using dual supply voltages, Proceedings of the 36th ACM/IEEE conference on Design automation, p.72-75, June 21-25, 1999, New Orleans, Louisiana, United States
	Chunhong Chen , Ankur Srivastava , Majid Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.616-629, October 2001
	Sung-Mo Kang, Elements of low power design for integrated systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Farhana Sheikh , Andreas Kuehlmann , Kurt Keutzer, Minimum-power retiming for dual-supply CMOS circuits, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Adit D. Singh, Low-power dual V_th pseudo dual V_dd domino circuits, Proceedings of the 17th symposium on Integrated circuits and system design, September 07-11, 2004, Pernambuco, Brazil
	Noureddine Chabini , Wayne Wolf, Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.6, p.573-589, June 2004
	Jeffrey A. Barnett, Dynamic Task-Level Voltage Scheduling Optimizations, IEEE Transactions on Computers, v.54 n.5, p.508-520, May 2005
	Sarvesh H. Kulkarni , Dennis Sylvester, Power distribution techniques for dual VDD circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Noureddine Chabini , Wayne Wolf, An approach for reducing dynamic power consumption in synchronous sequential digital designs, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.198-204, January 27-30, 2004, Yokohama, Japan
	Jatuchai Pangjun , Sachin S. Sapatnekar, Low-power clock distribution using multiple voltages and reduced swings, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.309-318, June 2002
	Mikhail Popovich , Eby G. Friedman , Michael Sotman , Avinoam Kolodny, On-chip power distribution grids with multiple supply voltages for high performance integrated circuits, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Yongseok Cheon , Pei-Hsin Ho , Andrew B. Kahng , Sherief Reda , Qinke Wang, Power-aware placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Noureddine Chabini , Ismaïl Chabini , El Mostapha Aboulhamid , Yvon Savaria, Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Abdulkadir U. Diril , Yuvraj S. Dhillon , Abhijit Chatterjee , Adit D. Singh, Low-power domino circuits using NMOS pull-up on off-critical paths, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Jun Cheng Chi , Hung Hsie Lee , Sung Han Tsai , Mely Chen Chi, Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.6, p.637-648, June 2007
	Mikhail Popovich , Eby G. Friedman , Michael Sotman , Avinoam Kolodny, On-chip power distribution grids with multiple supply voltages for high-performance integrated circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.908-921, July 2008