Survey of low power techniques for ROMs

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Survey of low power techniques for ROMs

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 7 - 11

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Edwin de Angel	Crystal Semiconductor Corporation, P.O. Box 17847, Austin, TX
Earl E. Swartzlander, Jr.	Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 31, Citation Count: 7

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. P. Chandrakasan, S. Sheng and R. W. Brodersen, "Low- Power CMOS Digital Design," IEEE Journal of Solid-State Circuits, vol. 27, pp. 473-483, 1992.
	2	D.A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits, Second edition, McGraw-Hill Publishing Company. pp. 346-353, 1988.
	3	M. Yoshimito, K.Anami, H. Shinohara, T. Yoshihara, H. Takagi, S. Nagao, S. Kayano, and T. Nakano, "A Divided Word- Line Structure in the Static RAM and its Application to a 64K Full CMOS RAM," IEEE Journal of Solid-State Circuits, vol. SC- 18, pp. 479-485, 1983.
	4	N. Sankarayya , K. Roy , D. Bhattacharya, Algorithms for Low Power FIR Filter Realization Using Differential Coefficients, Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, p.174, January 04-07, 1997
	5	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	6	C. Piguet, "Low-Power Microprocessors and Memories," NATO Seminar on Low Power Design in Deep Submicro Electronics, Lucca, Tuscany, Italy, August 20-30, 1996.
	7	E. de Angel and E. E. SwartzlanderJr., "Survey of Techniques for Low Power VLSI Design," International Conference on Innovative Systems in Silicon, pp. 159-169, 1996.
	8	R. C. Jaeger, "Comments on 'An optimized output state for MOS integrated circuits,' "IEEE Journal of Solid-State Circuits, vol. 10, pp. 185-186, 1975.
	9	G.L. HavilandandA. A. Tuszynski,"CMOS Tapered Buffer," IEEE Journal of Solid-State Circuits, vol. 25, pp. 1005-1008, 1990.
	10	J. Choi and K. Lee, "Design of CMOS Tapered Buffer for Minimum Power-Delay Product," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1142- 1145, 1994.
	11	H. J. Veendrick, "Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits," IEEE Journal of Solid-State Circuits, vol. SC-19, pp. 468- 473, 1984.
	12	M. Santoro, Design and Clocking of VLSI Multipliers, Ph.D. Dissertation, Stanford University, 1990.
	13	J. Figueras,"Power Modeling," NATO Semidar on Low Power Design in Deep Submicro Electronics, Lucca, Tuscany, italy, August 20-30, 1996.
	14	Charlie X. Huang , Bill Zhang , An-Chang Deng , Burkhard Swirski, The design and implementation of PowerMill, Proceedings of the 1995 international symposium on Low power design, p.105-110, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224100]

CITED BY 7

	John R. Sacha , Mary Jane Irwin, The logarithmic number system for strength reduction in adaptive filtering, Proceedings of the 1998 international symposium on Low power electronics and design, p.256-261, August 10-12, 1998, Monterey, California, United States
	Tohru Ishihara , Kunihiro Asada, A system level memory power optimization technique using multiple supply and threshold voltages, Proceedings of the 2001 conference on Asia South Pacific design automation, p.456-461, January 2001, Yokohama, Japan
	G. Chen , R. Shetty , M. Kandemir , N. Vijaykrishnan , M. J. Irwin , M. Wolczko, Tuning garbage collection for reducing memory system energy in an embedded java environment, ACM Transactions on Embedded Computing Systems (TECS), v.1 n.1, p.27-55, November 2002
	Hojun Shim , Yongsoo Joo , Yongseok Choi , Hyung Gyu Lee , Naehyuck Chang, Low-energy off-chip SDRAM memory systems for embedded applications, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.1, p.98-130, February 2003
	Tohru Ishihara , Hiroto Yasuura, A power reduction technique with object code merging for application specific embedded processors, Proceedings of the conference on Design, automation and test in Europe, p.617-623, March 27-30, 2000, Paris, France
	Byung-Do Yang , Lee-Sup Kim, A low-power charge-recycling ROM architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.590-598, August 2003
	Byung-Do Yang , Lee-Sup Kim, A low-power ROM using single charge-sharing capacitor and hierarchical bit line, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.4, p.313-322, April 2006

Collaborative Colleagues:

Edwin de Angel: colleagues

Earl E. Swartzlander, Jr.: colleagues

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