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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE J. Solid-State Circuits, vol. 25, no, 2, pp. 584-59 4, Apr. 1990.
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T.Sakurai & T.Kuroda, "Low-Power Circuit Design for Multimedia CMOS VLSI's," SASIMI, pp.3-10, Nov. 1996,
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S. Mutoh, et al., "IV High-Speed Digital Circuit Technology with 0.5pro Multi-Threshold CMOS~" in Proe. IEEE 1993 ASIC Conf., 1993, pp. 186-189.
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4
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S. Mutoh, et al.," 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," JSSC, vol. 30, no. 8, pp. 847-854, Aug. 1995.
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T. Kobayashi, and T. Sakurai, "Self-Adjusting Threshold- Voltage Scheme (SATS) for Low-Voltage High-Speed Operation," in Proe. IEEE 1994 CICC, May 1994, pp. 271-274.
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K.Seta, H.Hara, T.Kuroda, M. Kakumu and T.Sakurai, "50% Active Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit", in ISSCC Dig. Teeh. Papers, pp, 318-319, Feb., 1995.
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7
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T.Kuroda, T.Fujita, S.Mita, T.Nagamatsu, S.Yoshioka, F, Sano, M.Norishima, M.Murota, M.Kato, M.Kinugawa, M, Kakumu, and T.Sakurai, "A 0.9V 150MHz 10roW 4ram2 2-D discrete cosine transform core processor with variable-thresholdvoltage scheme," IEEE J. Solid-State Circuits, vol, 31, no, 11, Nov. 1996.
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8
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T.Kuroda, T.Fujita, T.Nagamatsu, S.Yoshioka, T.Sei, K, Matsuo, Y.Hamum, T.Mori, M.Murota, M.Kakumu, and T, Sakurai, "A High-Speed Low-Power 0.3/~m CMOS Gate Array with Variable Threshold Voltage (VT) Scheme," CICC'96, paper# 4.2, May 1996.
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Tadahiro Kuroda , Tetsuya Fujita , Shinji Mita , Toshiaki Mori , Kenji Matsuo , Masakazu Kakumu , Takayasu Sakurai, Substrate noise influence on circuit performance in variable threshold-voltage scheme, Proceedings of the 1996 international symposium on Low power electronics and design, p.309-312, August 12-14, 1996, Monterey, California, United States
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M. Mizuno, et al., "Elastic Vt CMOS circuits for multiple on chip power control," in ISSCC Dig. Teeh. Papers, Feb. 1996, pp, 3 00-301.
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H .Mizuno, et al., "A Lean-Power Gigaseale LSI using Hierarchical VBB Routing Scheme with Frequency Adaptive VT CMOS," Symp. On VLSI Circ., pp.95-96, June 1997,
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H.Kawaguchi & T.Sakurai "A Reduced Clock-Swing Flip. Flop (RCSFF) for 63% Clock Power Reduction," Syrup, On VLSI Circ., 15.2, June 1997.
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J.Montanaro et al., "A 160-Mhz, 32-b, 0.5-W CMOS RISC Microprocessor," JSSC, vol. 31, pp. 1703-1714, Nov, 1996,
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14
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M. Matsui, H.Hara, K.Seta, Y.Uetani, L.Kim, T.Nagamatsu, T.Shimazawa, S.Mita, G.Otomo, T.Oto, Y.Watanabe, F, Sano, A, Chiba, K.Matsuda and T.Sakurai, "200MHz Video Compression Macroeells Using Low-Swing Differential Logic," in ISSCC Dig, Tech. Papers, pp. 76-77, Feb., 1994.
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T.Sakurai "Approximation of Wiring Delay in MOSFEr LSI," JSSC, SC-18, No.4, pp.418-426, Aug. 1983.
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CITED BY 8
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Bhaskar Chatterjee , Manoj Sachdev , Steven Hsu , Ram Krishnamurthy , Shekhar Borkar, Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
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Daniel J. Deleganes , Micah Barany , George Geannopoulos , Kurt Kreitzer , Anant P. Singh , Sapumal Wijeratne, Low voltage swing logic circuits for a Pentium® 4 processor integer core, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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