Reconfigurable scan chains

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Reconfigurable scan chains: a novel approach to reduce test application time

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 710 - 715

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Sridhar Narayanan	Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA
Melvin A. Breuer	Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, CA

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sean P. Morley , Ralph Marlett, Selectable Length Partial Scan: A Method to Reduce Vector Length, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.385-392, October 26-30, 1991
	2	Y.-H. Choi , T. Jung, Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.13-16, November 1992, Santa Clara, California, United States
	3	IEEE Standard 1149.1-1990. IEEE Standard Test Access Port and Boundary Scan Architecture. IEEE Standards Board, New York, N.Y., 1990.
	4	M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Computer Science Press, New York, N.Y., 1990.
	5	S. Narayanan and M.A. Breuer. Reeonfiguration Techniques for a Single Scan Chain. Ivtternal report, Univ. of Southelaa California, June 1993.
	6	K.R. Baker. introduction to Sequencing and Scheduling. J.Wiley & Sons, Inc., 1974.
	7	R. Jain , K. Kücükcakar , M. J. Mlinar , A. C. Parker, Experience with ADAM synthesis system, Proceedings of the 26th ACM/IEEE conference on Design automation, p.56-61, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74393]
	8	R. Gupta , M. A. Breuer, The Ballast Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, v.39 n.4, p.538-544, April 1990 [doi>10.1109/12.54846]

CITED BY 2

	Sujit Dey , Miodrag Potkonjak, Non-scan design-for-testability of RT-level data paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.640-645, November 06-10, 1994, San Jose, California, United States
	Subhrajit Bhattacharya , Sujit Dey , Bhaskar Sengupta, An RTL Methodology to Enable Low Overhead Combinational Testing, Proceedings of the 1997 European conference on Design and Test, p.146, March 17-20, 1997

Collaborative Colleagues:

Sridhar Narayanan: colleagues

Melvin A. Breuer: colleagues

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