A spacing algorithm for performance enhancement and cross-talk reduction

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A spacing algorithm for performance enhancement and cross-talk reduction

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 697 - 702

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Kamal Chaudhary	Electronics Research Laboratory, University of California, Berkeley
Akira Onozawa	NTT LSI Laboratories, Atsugi, Kanagawa, Japan
Ernest S. Kuh	Electronics Research Laboratory, University of California, Berkeley

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 10, Citation Count: 17

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H.B. Bakoglu. Circuits, lnterconnections, and Packagingfor VLSI. Addison-Wesley Publishing Company, 1990.
	2	A. Srinivasan, K. Chaudhary, and E.S. Kuh. RITUAL : A performance driven placement algorithm. IEEE Trans. Circuits and Systems, pages 825-839, November 1992.
	3	S. Prasitjutrakul and W. J. Kubitz. A performance-driven global router for custom VLSI chip design. IEEE Trans. Computer-Aided Design, 11 (8): 1044-1051, August 1992.
	4	David G. Boyer, Symbolic layout compaction review, Proceedings of the 25th ACM/IEEE conference on Design automation, p.383-389, June 12-15, 1988, Atlantic City, New Jersey, United States
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	6	K. Nishimura and Y. Ohtomo. Private communication. LSI Laboratories, 1992.
	7	Akira Onozawa, Layout compaction with attractive and repulsive constraints, Proceedings of the 27th ACM/IEEE conference on Design automation, p.369-374, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123308]
	8	R. B. Hitchcock, G. L. Smith, and D. D. Cheng. Timing analysis of computer hardware. IBM Journal of Research and Development, 26(1 ): 100-105, 1983.
	9	T. Sakurai and K. Tamaru. Simple formulas for two- and three- dimensional capacitances. IEEE Trans. on Electron Devices, ED-30:183-185, Feb. 1983.
	10	K. Murty. Linear Programming. John Wiley and Sons, 1983.
	11	A. Feller, H.R. Kaupp, and J.J. Digiacomo. Crosstalk and reflections in high-speed digital systems. In AFIPS proceedings, volume 27, pages 511-525, 1965.
	12	T.Sakurai, S.Kobayashi, and M.Noda. Simple expressions for interconnection delay, coupling and crosstalk in VLSI's. In Proc. ISCAS, pages 2375-2378, 1991.
	13	Shen Lin , M. Marek-Sadowska , Ernest S. Kuh, SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	14	Y.-z. Liao and C. K. Wong. An algorithm to compact a VLSI symbolic layout with mixed constraints. IEEE Trans. Computer-Aided Design, CAD-2(2):62--69, April 1983.

CITED BY 17

	Hsiao-Ping Tseng , Louis Scheffer , Carl Sechen, Timing and crosstalk driven area routing, Proceedings of the 35th annual conference on Design automation, p.378-381, June 15-19, 1998, San Francisco, California, United States
	Hai Zhou , D. F. Wong, An optimal algorithm for river routing with crosstalk constraints, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.310-315, November 10-14, 1996, San Jose, California, United States
	Ki-Wook Kim , Unni Narayanan , Sung-Mo Kang, Domino logic synthesis minimizing crosstalk, Proceedings of the 37th conference on Design automation, p.280-285, June 05-09, 2000, Los Angeles, California, United States
	Joon-Seo Yim , Chong-Min Kyung, Reducing cross-coupling among interconnect wires in deep-submicron datapath design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.485-490, June 21-25, 1999, New Orleans, Louisiana, United States
	Hai Zhou , D. F. Wong, Optimal river routing with crosstalk constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.3, p.496-514, July 1998
	Prashant Saxena , C. L. Liu, Crosstalk minimization using wire perturbations, Proceedings of the 36th ACM/IEEE conference on Design automation, p.100-103, June 21-25, 1999, New Orleans, Louisiana, United States
	M. Seki , K. Kato , S. Kobayashi , K. Tsurusaki, A practical clock router that accounts for the capacitance derived from parallel and cross segments, Proceedings of the conference on European design automation, p.362-367, September 1996, Geneva, Switzerland
	Paul B. Morton , Wayne Dai, An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing, Proceedings of the 1999 international symposium on Physical design, p.22-28, April 12-14, 1999, Monterey, California, United States
	Desmond A. Kirkpatrick , Alberto L. Sangiovanni-Vincentelli, Techniques for crosstalk avoidance in the physical design of high-performance digital systems, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.616-619, November 06-10, 1994, San Jose, California, United States
	Tianxiong Xue , Ernest S. Kuh , Dongsheng Wang, Post global routing crosstalk risk estimation and reduction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.302-309, November 10-14, 1996, San Jose, California, United States
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware interconnect power optimization in domino logic synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.79-89, February 2003
	Y. Koolivand , A. Zahabi , N. Masoumi, Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Hai Zhou , D. F. Wong, Global routing with crosstalk constraints, Proceedings of the 35th annual conference on Design automation, p.374-377, June 15-19, 1998, San Francisco, California, United States
	Shanq-Jang Ruan , Edwin Naroska , Chun-Chih Chen, Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Chin-Chih Chang , Jason Cong, Pseudo pin assignment with crosstalk noise control, Proceedings of the 2000 international symposium on Physical design, p.41-47, May 2000, San Diego, California, United States
	Bassel Soudan, Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling, Analog Integrated Circuits and Signal Processing, v.43 n.2, p.191-203, May 2005
	Tsung-Yi Ho , Yao-Wen Chang , Sao-Jie Chen , D. T. Lee, A Fast Crosstalk- and Performance-Driven Multilevel Routing System, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.382, November 09-13, 2003

Collaborative Colleagues:

Kamal Chaudhary: colleagues

Akira Onozawa: colleagues

Ernest S. Kuh: colleagues

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