An algorithm for improving partitions of pin-limited multi-chip systems

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An algorithm for improving partitions of pin-limited multi-chip systems

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 378 - 385

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Mark Beardslee	University of California, Berkeley, CA
Alberto Sangiovanni-Vincentelli	University of California, Berkeley, CA

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 0

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. Kring mad A. R. Newton. A cell-replicating approach to mincut based circuit partitioning. In International Con- }erence on Computer-Aided Design, November 1991.
	2	Mark Beardslee , Bill Lin , Alberto Sangiovanni-Vincentelli, Communication based logic partitioning, Proceedings of the conference on European design automation, p.32-37, November 1992, Congress Centrum Hamburg, Hamburg, Germany
	3	T. Hwang, R.M. Owens, and M.J. Irwin. Exploiting communication complexity for multi-level logic synthesis. IEEE Transactions on Computer-Aided Design, 9(10):1017-1027, October 1990.
	4	R.M. Karp. Function decomposition and switching circuit design. Journal of Society of Industrial Applied Mathematics, 11(2), June 1963.
	5	B. Lin and A.R. Newton. Efficient symbolic manipulation of equivalence relations and classes. In International Workshop on Formal Methods in VLSI Design, December 1990.
	6	J. H. Tracey. Internal state assignments for asynchronous sequential machines. IEE~, Transactions on Electronic Computers, EC-15(4):551-560, August 1966.
	7	R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. MIS: A mu}itiple-level logic optimization system. IEEE Transaction~ on Computer-Aided Design, CAD-6(6):1062-1081, November 1987.
	8	T. Villa , A. Sangiovanni-Vincentelli, NOVA: state assignment of finite state machines for optimal two-level logic implementations, Proceedings of the 26th ACM/IEEE conference on Design automation, p.327-332, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74437]
	9	R.K. Brayton and F. Somenzi. Boolean relations and the incomplete specification of logic networks. In IFIP Int ernational Conference on Very Large Scale Integration, August 1989.
	10	R. K. Brayton and F. Somenzi. An exact minimizer for boolean relations. In International Conference on Computer-Aided Design, pages 316-319, November 1989.
	11	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	12	S. Malik, Albert R. Wang, Robert K. Brayton, and Alberto Sangiovanni-vincentelii. Logic verification using binary decision diagrams in e~ logic synthesis environment. In International Conference on Computer-Aided Design, November 1988.
	13	S. Kirkpatrick, C. Gelatt, Jr., and M. vecchi. Optimization by simulated annealing. Science, 220:671-680, May 1983.
	14	Xilinx Programmable Gate Array User' Guide. Xilinx Inc., 198D.

Collaborative Colleagues:

Mark Beardslee: colleagues

Alberto Sangiovanni-Vincentelli: colleagues

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