Minimum padding to satisfy short path constraints

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Minimum padding to satisfy short path constraints

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 156 - 161

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Narendra V. Shenoy	University of California, Berkeley, CA
Robert K. Brayton	University of California, Berkeley, CA
Alberto L. Sangiovanni-Vincentelli	University of California, Berkeley, CA

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 28, Citation Count: 18

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M.R.C.M. Berkelaar and J. A. G. Jess. Private communication. June, 1993.
	2	C. Leonard Berman , J. Lawrence Carter , Ken F. Day, The fanout problem: from theory to practice, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.69-99, June 1989, Cambridge, Massachusetts, United States
	3	John P. Fishburn, A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between, Proceedings of the 27th ACM/IEEE conference on Design automation, p.361-364, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123305]
	4	J. P. Fishburn, LATTIS: an iterative speedup heuristic for mapped logic, Proceedings of the 29th ACM/IEEE conference on Design automation, p.488-491, June 08-12, 1992, Anaheim, California, United States
	5	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	6	P.G. Paulin and F. Poirot. Logic Decompostion Algorithms for the Timing Optimization of Multi-Level Logic. In Proceedings of the International Conference on Computer Destgn, pages 329-33, 1989.
	7	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Resynthesis of multi-phase pipelines, Proceedings of the 30th international conference on Design automation, p.490-496, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164995]
	8	N. V. Shenoy. Timing Issues in Sequential Circuits. PhD thesis, University of California, Berkeley, 1993.
	9	K.J. Singh, A. R. Wang, R. K. Brayton, andA. Sangiovanni- V'mcentelli. Timing Optimization of Combinational Logic. In Proceedings of the International Conference on Computer-Aided Design, pages 282-285, 1988.
	10	Herve Jacques Touati, Performance-oriented technology mapping, University of California at Berkeley, Berkeley, CA, 1991
	11	D. Wong, G. De Mieheli, and M. Flynn. Inserting Active Delay Elements to Achieve Wave Pipelining. In Proceedings of the International Conference on Computer-Aided Design, pages 270-273. IEEE, 1989.

CITED BY 18

	Harsha Sathyamurthy , Sachin S. Sapatnekar , John P. Fishburn, Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.467-470, November 05-09, 1995, San Jose, California, United States
	Rahul B. Deokar , Sachin S. Sapatnekar, A fresh look at retiming via clock skew optimization, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.310-315, June 12-16, 1995, San Francisco, California, United States
	Marios C. Papaefthymiou, Asymptotically efficient retiming under setup and hold constraints, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.396-401, November 08-12, 1998, San Jose, California, United States
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, Marsh: min-area retiming with setup and hold constraints, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.2-6, November 07-11, 1999, San Jose, California, United States
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Sung-Mo Kang, Minimum delay optimization for domino logic circuits---a coupling-aware approach, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.2, p.203-213, April 2003
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.3, p.273-289, July 2004
	Mitrajit Chatterjee , Savita Banerjee , Dhiraj K. Pradhan, Buffer Assignment Algorithms on Data Driven ASICs, IEEE Transactions on Computers, v.49 n.1, p.16-32, January 2000
	Baris Taskin , Ivan S. Kourtev, Delay insertion method in clock skew scheduling, Proceedings of the 2005 international symposium on Physical design, April 03-06, 2005, San Francisco, California, USA
	Shih-Hsu Huang , Yow-Tyng Nieh , Feng-Pin Lu, Race-condition-aware clock skew scheduling, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Chuan Lin , Hai Zhou, An efficient retiming algorithm under setup and hold constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	V. Seth , Min Zhao , Jiang Hu, Exploiting level sensitive latches in wire pipelining, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.283-290, November 07-11, 2004
	R. Fung , V. Betz , W. Chow, Simultaneous short-path and long-path timing optimization for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.838-845, November 07-11, 2004
	Shih-Hsu Huang , Yow-Tyng Nieh, Clock Period Minimization of Non-Zero Clock Skew Circuits, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.809, November 09-13, 2003
	Shih-Hsu Huang , Yow-Tyng Nieh, Clock skew scheduling with race conditions considered, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.45-es, September 2007
	Zhengtao Yu , Xun Liu, Design of rotary clock based circuits, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Yu-Shih Su , Po-Hsien Chang , Shih-Chieh Chang , Tingting Hwang, Synthesis of a novel timing-error detection architecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.1, p.1-14, January 2008
	Shih-Hsu Huang , Chun-Hua Cheng , Chia-Ming Chang , Yow-Tyng Nieh, Clock period minimization with minimum delay insertion, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Hyein Lee , Seungwhun Paik , Youngsoo Shin, Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California

Collaborative Colleagues:

Narendra V. Shenoy: colleagues

Robert K. Brayton: colleagues

Alberto L. Sangiovanni-Vincentelli: colleagues

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