Combining technology mapping and placement for delay-optimization in FPGA designs

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Combining technology mapping and placement for delay-optimization in FPGA designs

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 123 - 127

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Chau-Shen Chen	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
Yu-Wen Tsay	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
TingTing Hwang	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
Allen C. H. Wu	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.
Youn-Long Lin	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 10

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	2	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
	3	Kevin Karplus, Xmap: A technology mapper for table-lookup field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.240-243, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127672]
	4	R. 3. Francis, J. Rose, and Z. Vranesic, "Technology Mapping of Lookup Table-Based FPGA.,~ for Performance," Proc. int'l Conf. Computer-Aided Design, pp. 568-571, Nov., i991.
	5	R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures," Proc. Int'l Conf. Computer-aided Design, Nov., 1991
	6	R. Murgai, N. Shenoy, R. K. Biayton, and A. Sangiovanni-Vincentelli, "Performance Directed Synthesis for Table Look Up Programmable Gate Arrays," Proc. Int'l Conf. Computer-aided Design, Nov., 1991
	7	Christos H. Papadimitriou , Kenneth Steiglitz, Combinatorial optimization: algorithms and complexity, Prentice-Hall, Inc., Upper Saddle River, NJ, 1982
	8	Kuang-Chien Chen , Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar, DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization, IEEE Design & Test, v.9 n.3, p.7-20, July 1992 [doi>10.1109/54.156154]
	9	Jason Cong , Yuzheng Ding, An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.48-53, November 1992, Santa Clara, California, United States

CITED BY 10

	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996
	Andreas Koch, Module compaction in FPGA-based regular datapaths, Proceedings of the 33rd annual conference on Design automation, p.471-476, June 03-07, 1996, Las Vegas, Nevada, United States
	Jason Cong , Songjie Xu, Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs, Proceedings of the 2000 conference on Asia South Pacific design automation, p.157-162, January 2000, Yokohama, Japan
	Tanay Karnik , Sung-Mo Kang, An empirical model for accurate estimation of routing delay in FPGAs, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.328-331, November 05-09, 1995, San Jose, California, United States
	Honghua Yang , D. F. Wong, Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.150-155, November 06-10, 1994, San Jose, California, United States
	Nozomu Togawa , Masao Sato , Tatsuo Ohtsuki, A simultaneous technology mapping, placement, and global routing algorithm for field-programmable gate arrays, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.156-163, November 06-10, 1994, San Jose, California, United States
	Taraneh Taghavi , Soheil Ghiasi , Abhishek Ranjan , Salil Raje , Majid Sarrafzadeh, Innovate or perish: FPGA physical design, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Andreas Koch, Structured design implementation: a strategy for implementing regular datapaths on FPGAs, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.151-157, February 11-13, 1996, Monterey, California, United States
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Maogang Wang , Abhishek Ranjan , Salil Raje, Multi-Million Gate FPGA Physical Design Challenges, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.891, November 09-13, 2003

Collaborative Colleagues:

Chau-Shen Chen: colleagues

Yu-Wen Tsay: colleagues

TingTing Hwang: colleagues

Allen C. H. Wu: colleagues

Youn-Long Lin: colleagues

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