Cube-packing and two-level minimization

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Cube-packing and two-level minimization

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 115 - 122

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Rajeev Murgai	Department of EECS, University of California, Berkeley, CA
Robert K. Brayton	Department of EECS, University of California, Berkeley, CA
Alberto Sangiovanni-Vincentelli	Department of EECS, University of California, Berkeley, CA

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Xilinx inc., 2069, Hamilton Ave. San Jose, CA-95125, The Programmable Gate Array Data Book.
	2	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	3	R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "MIS: A Multiple-Level Logic Optimization System", IEEE Transactions on CAD, November 1987.
	4	Garey and Johnson, "Computers and Intractability", Freeman, San Francisco, CA, 197'9.
	5	Robert J. Francis , Jonathan Rose , Kevin Chung, Chortle: a technology mapping program for lookup table-based field programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.613-619, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123418]
	6	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
	7	Rajeev Murgai , Yoshihito Nishizaki , Narendra Shenoy , Robert K. Brayton , Alberto Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.620-625, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123421]
	8	R. Murgai, N. Shenoy, R. K. Brayton and A. Sangiovanni- Vincentelli, "Improved Logic Synthesis Algorithms for Table Look Up Architectures", Internal Report, University of California, Berkeley, 1991.
	9	M. Fujita and Y. Matsunaga, "Multi-level Logic Minimization based on Minimal Support and its Application to the Minimization of Look-up Table Type FPGAs", in Proceedings of the International Conference on Computer-Aided Design, 1991.
	10	C. Halatsis and N. Gaitanis, "irredundant Normal Forms and Minimal Dependence Sets of a Boolean Function", in IEEE Transactions on Computers, pages 1064-1068, November 1978.
	11	David Filo , Jerry Chih-Yuan Yang , Frédéric Mailhot , Giovanni De Micheli, Technology mapping for a two-output RAM-based field programmable gate array, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	12	Kevin Karplus, Amap: A technology mapper for selector-based field-programmable gate arrays, Proceedings of the 28th conference on ACM/IEEE design automation, p.244-247, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127673]
	13	P. Sicard, M. Crastes, K. Sakouti, and G. Saucier, "Automatic Synthesis of Boolean Functions on Xilinx and Actel Programmable Devices", in Euro ASIC, pages 142-145, May 1991.
	14	Nam-Sung Woo, A heuristic method for FPGA technology mapping based on the edge visibility, Proceedings of the 28th conference on ACM/IEEE design automation, p.248-251, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127675]
	15	R. L. Rudell, "Logic Synthesis for VLSI Design", UCB/BRL Memorandum M89/~$9, April 1989.
	16	J. Gimpel, "A Reduction technique for prime implicant tables", IEEE Transactions Elec. Comp., EC-14:535-541, August 1965.
	17	J.P. Roth and R.M. Karp, "Minimization over Boolean graphs", IBM Journal of Research and Development, April 1962.
	18	H. Savoj, H. Touati and R. K. Brayton, "Extracting Local Don't cares for Network Optimization", in Proceedings of the International Conference on Computer-Aided Design, 1991.
	19	Patrick McGeer , Jagesh Sanghavi , Robert Brayton , Alberto Sangiovanni Vincentelli, Espresso-signature: a new exact minimizer for logic functions, Proceedings of the 30th international conference on Design automation, p.618-624, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165069]

Collaborative Colleagues:

Rajeev Murgai: colleagues

Robert K. Brayton: colleagues

Alberto Sangiovanni-Vincentelli: colleagues

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