Interleaving based variable ordering methods for ordered binary decision diagrams

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Interleaving based variable ordering methods for ordered binary decision diagrams

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 38 - 41

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Hiroshige Fujii	ULSI Research Laboratories, Research and Development Center, Toshiba Corporation, Kawasaki 210, Japan
Goichi Ootomo	ULSI Research Laboratories, Research and Development Center, Toshiba Corporation, Kawasaki 210, Japan
Chikahiro Hori	ULSI Research Laboratories, Research and Development Center, Toshiba Corporation, Kawasaki 210, Japan

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 36, Citation Count: 20

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	2	S. Malik, A. R. Wang, R. K. Brayton, and A. Sangiovanni- Vincentelli, "Logic Verification using Binary Decision Diagrams in a Logic Synthesis Environment," in Proc. of International Conference on Computer-Aided Design, pp.6-8, 1988.
	3	Karl S. Brace , Richard L. Rudell , Randal E. Bryant, Efficient implementation of a BDD package, Proceedings of the 27th ACM/IEEE conference on Design automation, p.40-45, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123222]
	4	M. Fujita, H. Fujisawa, and Y. Matsunaga, "Variable Ordering Algorithms for Ordered Binary Decision Diagrams and Their Evaluation," IEEE Trans. Computer-Aided Design, vol. 12, pp.6-12, Jan. 1993.
	5	Shin-ichi Minato , Nagisa Ishiura , Shuzo Yajima, Shared binary decision diagram with attributed edges for efficient Boolean function manipulation, Proceedings of the 27th ACM/IEEE conference on Design automation, p.52-57, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123225]
	6	F. Brgtez and H. Fujiwara, "A neutral netlist of 10 cx~mbinational benchmark circuits and a target translator in Fortran," in Proc. of Intemational Symposium on Circuit and Systems, 1985.
	7	Masahiro Fujita , Yusuke Matsunaga , Taeko Kakuda, On variable ordering of binary decision diagrams for the application of multi-level logic synthesis, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	8	N. Ishiura, H. Sawada, and S. Yajima, "Minimization of binary decision diagrams based on exchange of variables," in Proc. of International Conference on Computer-Aided Design, pp.472-475, 1991.
	9	M. R. Mercer , R. Kapur , D. E. Ross, Functional approaches to generating orderings for efficient symbolic representations, Proceedings of the 29th ACM/IEEE conference on Design automation, p.624-627, June 08-12, 1992, Anaheim, California, United States
	10	F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," in Ploc. of International Symposium on Circuit and Systems, pp.1929-1934, 1989.

CITED BY 20

	Rüdiger Ebendt , Rolf Drechsler, Lower bounds for dynamic BDD reordering, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Chunghee Kim , Luciano Lavagno , Alberto Sangiovanni-Vincentelli, Free MDD-based software optimization techniques for embedded systems, Proceedings of the conference on Design, automation and test in Europe, p.14-19, March 27-30, 2000, Paris, France
	Adnan Aziz , Serdar Taşiran , Robert K. Brayton, BDD variable ordering for interacting finite state machines, Proceedings of the 31st annual conference on Design automation, p.283-288, June 06-10, 1994, San Diego, California, United States
	Christoph Scholl , Bernd Becker , Andreas Brogle, The multiple variable order problem for binary decision diagrams: theory and practical application, Proceedings of the 2001 conference on Asia South Pacific design automation, p.85-90, January 2001, Yokohama, Japan
	Rolf Drechsler , Nicole Drechsler , Wolfgang Günther, Fast exact minimization of BDDs, Proceedings of the 35th annual conference on Design automation, p.200-205, June 15-19, 1998, San Francisco, California, United States
	Rolf Drechsler , Wolfgang Günther, Using lower bounds during dynamic BDD minimization, Proceedings of the 36th ACM/IEEE conference on Design automation, p.29-32, June 21-25, 1999, New Orleans, Louisiana, United States
	Youpyo Hong , Peter A. Beerel , Jerry R. Burch , Kenneth L. McMillan, Safe BDD minimization using don't cares, Proceedings of the 34th annual conference on Design automation, p.208-213, June 09-13, 1997, Anaheim, California, United States
	Jawahar Jain , William Adams , Masahiro Fujita, Sampling schemes for computing OBDD variable orderings, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.631-638, November 08-12, 1998, San Jose, California, United States
	Edmund M. Clarke , Bernd-Holger Schlingloff, Model checking, Handbook of automated reasoning, Elsevier Science Publishers B. V., Amsterdam, The Netherlands, 2001
	Rolf Drechsler , Wolfgang Günther , Stefan Höreth, Minimization of word-level decision diagrams, Integration, the VLSI Journal, v.33 n.1, p.39-70, December 2002
	Stephan Merz, Model checking: a tutorial overview, Modeling and verification of parallel processes, Springer-Verlag New York, Inc., New York, NY, 2001
	A. Hett , B. Becker , R. Drechsler, MORE: an alternative implementation of BDD packages by multi-operand synthesis, Proceedings of the conference on European design automation, p.164-169, September 1996, Geneva, Switzerland
	Yu-Liang Wu , Hongbing Fan , Malgorzata Marek-Sadowska , C. k. Wong, OBDD Minimization Based on Two-Level Representation of Boolean Functions, IEEE Transactions on Computers, v.49 n.12, p.1371-1379, December 2000
	Rüdiger Ebendt , Wolfgang Günther , Rolf Drechsler, Combining ordered best-first search with branch and bound for exact BDD minimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.875-878, January 27-30, 2004, Yokohama, Japan
	Rolf Drechsler , Bernd Becker , Andrea Jahnke, On Variable Ordering and Decomposition Type Choice in OKFDDs, IEEE Transactions on Computers, v.47 n.12, p.1398-1403, December 1998
	Ziv Nevo , Monica Farkash, Distributed dynamic BDD reordering, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Elsa Loekito , James Bailey, Fast mining of high dimensional expressive contrast patterns using zero-suppressed binary decision diagrams, Proceedings of the 12th ACM SIGKDD international conference on Knowledge discovery and data mining, August 20-23, 2006, Philadelphia, PA, USA
	Rudiger Ebendt , Wolfgang Gunther , Rolf Drechsler, Combination of Lower Bounds in Exact BDD Minimization, Proceedings of the conference on Design, Automation and Test in Europe, p.10758, March 03-07, 2003
	A. Hett , R. Drechsler , B. Becker, Fast and Efficient Construction of BDDs by Reordering Based Synthesis, Proceedings of the 1997 European conference on Design and Test, p.168, March 17-20, 1997
	Orna Grumberg , Shlomi Livne , Shaul Markovitch, Learning to order BDD variables in verification, Journal of Artificial Intelligence Research, v.18 n.1, p.83-116, January 2003

Collaborative Colleagues:

Hiroshige Fujii: colleagues

Goichi Ootomo: colleagues

Chikahiro Hori: colleagues

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