An improved method for RTL synthesis with testability tradeoffs

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An improved method for RTL synthesis with testability tradeoffs

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 30 - 35

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Haidar Harmanani	Department of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
Christos A. Papachristou	Department of Computer Engineering, Case Western Reserve University, Cleveland, Ohio

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 17

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 17

	Sujit Dey , Miodrag Potkonjak, Non-scan design-for-testability of RT-level data paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.640-645, November 06-10, 1994, San Jose, California, United States
	Han Bin Kim , Dong Sam Ha , Takeshi Takahashi, On ILP formulations for built-in self-testable data path synthesis, Proceedings of the 36th ACM/IEEE conference on Design automation, p.742-747, June 21-25, 1999, New Orleans, Louisiana, United States
	Ishwar Parulkar , Sandeep Gupta , Melvin A. Breuer, Data path allocation for synthesizing RTL design with low BIST area overhead, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.395-401, June 12-16, 1995, San Francisco, California, United States
	Mehrdad Nourani , Christos A. Papachristou, False path exclusion in delay analysis of RTL structures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.30-43, 2/1/2002
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Introducing redundant computations in RTL data paths for reducing BIST resources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.423-445, July 2001
	I. Parulkar , S. K. Gupta , M. A. Breuer, Scheduling and module assignment for reducing BIST resources, Proceedings of the conference on Design, automation and test in Europe, p.66-73, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Kenneth D. Wagner , Sujit Dey, High-level synthesis for testability: a survey and perspective, Proceedings of the 33rd annual conference on Design automation, p.131-136, June 03-07, 1996, Las Vegas, Nevada, United States
	Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel, Enhancing high-level control-flow for improved testability, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.322-328, November 10-14, 1996, San Jose, California, United States
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Lower bounds on test resources for scheduled data flow graphs, Proceedings of the 33rd annual conference on Design automation, p.143-148, June 03-07, 1996, Las Vegas, Nevada, United States
	J. C. Wang , P. S. Cardoso , J. A. Q. Gonzalez , M. Strum , R. Pires, Datapath BIST Insertion Using Pre-Characterized Area and Testability Data, Journal of Electronic Testing: Theory and Applications, v.20 n.4, p.333-344, August 2004
	P. Bukovjan , L. Ducerf-Bourbon , M. Marzouki, Cost/Quality Trade-off in Synthesis for BIST, Journal of Electronic Testing: Theory and Applications, v.17 n.2, p.109-119, April 2001
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Introducing redundant computations in a behavior for reducing BIST resources, Proceedings of the 35th annual conference on Design automation, p.548-553, June 15-19, 1998, San Francisco, California, United States
	Sujit Dey , Anand Raghunathan , Kenneth D. Wagner, Design for Testability Techniques at the Behavioraland Register-Transfer Levels, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.79-91, Oct. 1998
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Allocation Techniques for Reducing BIST Area Overhead ofData Paths, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.149-166, Oct. 1998
	Christos A. Papachristou , Mikhail Baklashov , Kowen Lai, High-Level Test Synthesis for Behavioral and Structural Designs, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.167-188, Oct. 1998
	Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer, Estimation of BIST Resources During High-Level Synthesis, Journal of Electronic Testing: Theory and Applications, v.13 n.3, p.221-237, Dec. 1998
	Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel, Testability Insertion in Behavioral Descriptions, Proceedings of the 9th international symposium on System synthesis, p.139, November 06-08, 1996

Collaborative Colleagues:

Haidar Harmanani: colleagues

Christos A. Papachristou: colleagues

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