Exploiting hardware sharing in high-level synthesis for partial scan optimization

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Exploiting hardware sharing in high-level synthesis for partial scan optimization

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International Conference on Computer Aided Design archive
Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 20 - 25

Year of Publication: 1993

ISBN:0-8186-4490-7

Authors

Sujit Dey	C&C Research Laboratories, NEC, Princeton, NJ
Miodrag Potkonjak	C&C Research Laboratories, NEC, Princeton, NJ
Rabindra K. Roy	C&C Research Laboratories, NEC, Princeton, NJ

Sponsors

IEEE-CS : Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 17, Citation Count: 15

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	2	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	3	D.H. Lee and S.M. Reddy. On Determining Scan Flip-Flops in Partial-Scan Designs. In Proceedings of the International Conference on Computer-Aided Design, pages 322 - 325, November 1990.
	4	V. Chickermane and L H. Patel. A Fault Oriented Partial Scan Design Approach. In Proceedings of the InternationalConference on Computer-Aided Design, pages 400 - 403, November 1991.
	5	Christos A. Papachristou , Scott Chiu , Haidar Harmanani, SYNTEST: A Method for High-Level SYNthesis with Self-TESTability, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.458-462, October 14-16, 1991
	6	Tien-Chien Lee , Wayne H. Wolf , Niraj K. Jha, Behavioral synthesis for easy testability in data path scheduling, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.616-619, November 1992, Santa Clara, California, United States
	7	Tien-Chien Lee , Niraj K. Jha , Wayne H. Wolf, Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments, Proceedings of the 30th international conference on Design automation, p.292-297, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164897]
	8	Chung-Hsing Chen , Daniel G. Saab, Behavioral synthesis for testability, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.612-615, November 1992, Santa Clara, California, United States
	9	A. Majumdar, K. Saluja, and R. Jain. Incorporating Testabihty Considerations in High-Level Synthesis. In Proceedings of the lnternational Symposium on Fault. Tolerant Computing, 1992.
	10	M.C. MeFadand, A.C. Parker, and R. Camposano. The High-Level Synthesis of Digital Systems. Proceedings of the IEEE, 78(2):301 - 317,1992.
	11	H. De Man et. al.. Synthesis of DSP Systems at Leuven. In Proc. of the IEEE ICCD, pages 133 - 145,1987.
	12	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]
	13	Leon Stok, False loops through resource sharing, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.345-348, November 1992, Santa Clara, California, United States
	14	S. Dey, M. Potkonjak, and R. Roy. Exploiting Hardware Sharing m High Level Synthesis for Partial Scan Optimization. Technical Report 93-C013, C&C Research Labs, NEC USA, April 1993.

CITED BY 15

	Sujit Dey , Vijay Gangaram , Miodrag Potkonjak, A controller-based design-for-testability technique for controller-data path circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.534-540, November 05-09, 1995, San Jose, California, United States
	Miodrag Potkonjak , Sujit Dey, Optimizing resource utilization and testability using hot potato techniques, Proceedings of the 31st annual conference on Design automation, p.201-205, June 06-10, 1994, San Diego, California, United States
	Kumar N. Lalgudi , Marios C. Papaefthymiou, DELAY: an efficient tool for retiming with realistic delay modeling, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.304-309, June 12-16, 1995, San Francisco, California, United States
	Frank F. Hsu , Janak H. Patel, High-level variable selection for partial-scan implementation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.79-84, November 08-12, 1998, San Jose, California, United States
	Clay Gloster , Franc Brglez, Partial scan selection for user-specified fault coverage, Proceedings of the conference on European design automation, p.111-116, September 18-22, 1995, Brighton, England
	Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel, Enhancing high-level control-flow for improved testability, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.322-328, November 10-14, 1996, San Jose, California, United States
	Inki Hong , Darko Kirovski , Miodrag Potkonjak, Potential-driven statistical ordering of transformations, Proceedings of the 34th annual conference on Design automation, p.347-352, June 09-13, 1997, Anaheim, California, United States
	Sujit Dey , Miodrag Potkonjak, Non-scan design-for-testability of RT-level data paths, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.640-645, November 06-10, 1994, San Jose, California, United States
	Saeed Safari , Amir Hossein Jahangir , Hadi Esmaeilzadeh, A parameterized graph-based framework for high-level test synthesis, Integration, the VLSI Journal, v.39 n.4, p.363-381, July 2006
	M. L. Flottes , D. Hammad , B. Rouzeyre, Improving Testability of Non-Scan Designs during BehavioralSynthesis, Journal of Electronic Testing: Theory and Applications, v.11 n.1, p.29-42, Aug. 1997
	Huy Nguyen , Rabindra Roy , Abhijit Chatterjee, Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.14 n.3, p.259-272, June 1999
	Frank F. Hsu , Janak H. Patel, High-Level Controllability and Observability Analysis for Test Synthesis, Journal of Electronic Testing: Theory and Applications, v.13 n.2, p.93-103, Oct. 1998
	Xinli Gu , Erik Larsson , Krzysztof Kuchinski , Zebo Peng, A Controller Testability Analysis and Enhancement Technique, Proceedings of the 1997 European conference on Design and Test, p.153, March 17-20, 1997
	Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel, Testability Insertion in Behavioral Descriptions, Proceedings of the 9th international symposium on System synthesis, p.139, November 06-08, 1996
	Margrit R. Krug , Marcelo S. Moraes , Marcelo S. Lubaszewski, Using a software testing technique to identify registers for partial scan implementation, Proceedings of the 19th annual symposium on Integrated circuits and systems design, August 28-September 01, 2006, Ouro Preto, MG, Brazil

Collaborative Colleagues:

Sujit Dey: colleagues

Miodrag Potkonjak: colleagues

Rabindra K. Roy: colleagues

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