Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models

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Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models

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ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures table of contents

Newport, Rhode Island, United States

Pages: 199 - 210

Year of Publication: 1997

ISBN:0-89791-890-8

Authors

Parthasarathy Ranganathan	Department of Electrical and Computer Engineering, Rice University, Houston, Texas
Vijay S. Pai	Department of Electrical and Computer Engineering, Rice University, Houston, Texas
Sarita V. Adve	Department of Electrical and Computer Engineering, Rice University, Houston, Texas

Sponsors

SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 34, Citation Count: 25

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 25

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	Xiaogang Qiu , Michel Dubois, Tolerating late memory traps in ILP processors, ACM SIGARCH Computer Architecture News, v.27 n.2, p.76-87, May 1999
	Victor Luchangco, Modeling weakly consistent memories with locks, Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures, p.332-333, July 2001, Crete Island, Greece
	Daniel J. Sorin , Milo M. K. Martin , Mark D. Hill , David A. Wood, SafetyNet: improving the availability of shared memory multiprocessors with global checkpoint/recovery, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Mark D. Hill, Multiprocessors Should Support Simple Memory-Consistency Models, Computer, v.31 n.8, p.28-34, August 1998
	Marco Galluzzi , Ramón Beivide , Valentin Puente , José-Ángel Gregorio , Adrian Cristal , Mateo Valero, Evaluating kilo-instruction multiprocessors, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.72-79, June 20-20, 2004, Munich, Germany
	Marco Galluzzi , Valentín Puente , Adrián Cristal , Ramón Beivide , José-Ángel Gregorio , Mateo Valero, A first glance at Kilo-instruction based multiprocessors, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
	Robert C. Steinke , Gary J. Nutt, A unified theory of shared memory consistency, Journal of the ACM (JACM), v.51 n.5, p.800-849, September 2004
	Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan, An analysis of a resource efficient checkpoint architecture, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.4, p.418-444, December 2004
	Jeremy Manson , William Pugh , Sarita V. Adve, The Java memory model, ACM SIGPLAN Notices, v.40 n.1, p.378-391, January 2005
	Zehra Sura , Xing Fang , Chi-Leung Wong , Samuel P. Midkiff , Jaejin Lee , David Padua, Compiler techniques for high performance sequentially consistent java programs, Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 15-17, 2005, Chicago, IL, USA
	Xiaogang Qiu , Michel Dubois, Tolerating Late Memory Traps in Dynamically Scheduled Processors, IEEE Transactions on Computers, v.53 n.6, p.732-743, June 2004
	Ravi Rajwar , James R. Goodman, Speculative lock elision: enabling highly concurrent multithreaded execution, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Albert Meixner , Daniel J. Sorin, Unified microprocessor core storage, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
	Luis Ceze , James Tuck , Pablo Montesinos , Josep Torrellas, BulkSC: bulk enforcement of sequential consistency, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Hans-J. Boehm , Sarita V. Adve, Foundations of the C++ concurrency memory model, ACM SIGPLAN Notices, v.43 n.6, June 2008
	Thomas F. Wenisch , Anastasia Ailamaki , Babak Falsafi , Andreas Moshovos, Mechanisms for store-wait-free multiprocessors, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Yuan Chou , Lawrence Spracklen , Santosh G. Abraham, Store Memory-Level Parallelism Optimizations for Commercial Applications, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.183-196, November 12-16, 2005, Barcelona, Spain
	Christoph von Praun , Harold W. Cain , Jong-Deok Choi , Kyung Dong Ryu, Conditional Memory Ordering, ACM SIGARCH Computer Architecture News, v.34 n.2, p.41-52, May 2006
	Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan, Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.423, December 03-05, 2003
	Derek R. Hower , Mark D. Hill, Rerun: Exploiting Episodes for Lightweight Memory Race Recording, ACM SIGARCH Computer Architecture News, v.36 n.3, p.265-276, June 2008
	Pablo Montesinos , Luis Ceze , Josep Torrellas, DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Ef?ciently, ACM SIGARCH Computer Architecture News, v.36 n.3, p.289-300, June 2008
	Lee Baugh , Naveen Neelakantam , Craig Zilles, Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory, ACM SIGARCH Computer Architecture News, v.36 n.3, p.115-126, June 2008
	Andrew Hilton , Amir Roth, Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009
	Colin Blundell , Milo M.K. Martin , Thomas F. Wenisch, InvisiFence: performance-transparent memory ordering in conventional multiprocessors, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009