A FPGA-based implementation of a fault-tolerant neural architecture for photon identification

ABSTRACT

Event identification in photon counting ICCD detectors requires a high level image analysis which cannot be easily described algorithmically: neural networks are promising to approach this application. A system capable of identifying these events on board of satellites needs fault tolerant capabilities to certify result correctness. The rapid evolution of the problem specification, due to the increasing knowledge about the physics, makes attractive the availability and modifiability of prototypes: FPGA-based design is effective to realize these systems. The paper presents therefore an FPGA-based implementation of a fault tolerant neural architecture for event identification.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Neural nets

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Aerospace

General Terms:
Algorithms, Design, Performance