Synchronous up/down binary counter for LUT FPGAs with counting frequency independent of counter size

ABSTRACT

This paper presents the design of a fast binary counter for LUT FPGAs. The counter has a cycle time independent of the counter size. The key aspects of the design are described and applied to a 64-bit synchronous binary counter implemented in a XC4010 FPGA chip. Experimental results show that the counter can scale up to hundreds of bits while keeping a short cycle time.

REFERENCES

• 1: Ercegovac, M. D.; Lang, T.; Binary Counter with Counting Period of One Half Adder Independent of Counter Size;IEEE Transactions on Circuits and Systems, Vol. 36, No.6, 1989, pp. 924-926.
• 2: Milos D. Ercegovac , Jaime H. Moreno , Tomas Lang, Introduction to Digital Systems, John Wiley & Sons, Inc., New York, NY, 1998
• 3: Vuillemin, J. E.; Constant Time Arbitrary Length Synchronous Binary Counters; IEEE 10th Symposium on Computer Arithmetic, 199 I, pp. 180-183.
• 4: Xilinx; The Programmable Logic Data Book, August 1993.
• 5: Xililzx; The XC4000 Data Book; August 1992.
• 6: VCC- EVC1 - Engineer's Virtual Computer, User's Manual.
• 7: Stan, M. R. and Bufieson, W. P.; Synchronous Up/Down Counter with Period Independent of Counter Size; distributed at FPGA'96.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Arithmetic and logic units
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits

General Terms:
Algorithms, Design, Experimentation, Performance