Challenges in CAD for the one million gate FPGA

ABSTRACT

FPGA and CPLD densities have typically lagged their gate-array and standard-cell counterparts in effective density by a factor of 10. This means that the design problems encountered by ASIC designers will typically be encountered by FPGA designers 5-6 years later and tools used in the ASIC market to address them will ultimately be adopted by FPGA designers. Thus anyone familiar with the evolution of ASIC design tools can amaze and impress their FPGA-focussed friends with their ability to predict the future of FPGA design tools. In this short abstract we will outline the probable evolution of FPGA devices as they grow to one million gate-equivalents and then will chart the evolution of FPGA tool needs as they grow to meet the challenges of the million gate FPGA.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

General Terms:
Design, Performance, Verification