Wormhole run-time reconfiguration

ABSTRACT

Configurable Computing Machines (CCMs) are an emerging class of computing platform which provide the computational performance benefits of ASICs, yet retain the flexibility and rapid reconfigurability of general purpose microprocessors. In these platforms, computational "hardware" is essentially swapped in and out of the platform as needed, much like paging in virtual memory systems. For an efficient platform, the swapping of the computational hardware (referred to as Run-Time Reconfiguration, or RTR) must be rapid. Thus far, the means of altering the configuration of CCMs has relied on global control strategies that present a fundamental bottleneck to the potential bandwidth of configuration information flowing into the CCM. Wormhole Run-time Reconfiguration is presented as a distributed control methodology that is applicable not only to the problem of device-level CCM reconfiguration, but to system-wide concurrent computing as a whole. The Virginia Tech Colt/Stallion integrated circuits are computational FPGAs incorporating Wormhole RTR concepts, and are discussed as a case study.

REFERENCES

• 1: J. Eldredge and B. Hutchings, "Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration," in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, edited by D. Buell and K. Pocek, Napa, CA, pp. 180-188, April 1994.
• 2: The Programmable Logic Data Book. Xilinx Incorporated, San Jose, California, pp. 2-4- 243, 1994.
• 3: Altera 1995 Data Book. Altera Corporation, San Jose, California, pp. 37-93, 1995.
• 4: Tony Stansfield , Ian Page, The Design of a New FPGA Architecture, Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, p.1-14, September 01, 1995
• 5: C. Rupp, "CLAyFun Reference Manual," National Semiconductor Corporation, Santa Clara, California, July 1995.
• 6: Kai Hwang, Advanced Computer Architecture: Parallelism,Scalability,Programmability, McGraw-Hill Higher Education, 1992
• 7: W. J. Dally , C. L. Seitz, Deadlock-free message routing in multiprocessor interconnection networks, IEEE Transactions on Computers, v.36 n.5, p.547-553, May 1987 [doi>10.1109/TC.1987.1676939]
• 8: R. Bittner, M. Musgrove, P. Athanas, "Colt: An Experiment in Wormhole Run-Time Reconfiguration," to appear at Photonics East, Conference on High-Speed Computing, Digital Signal Processing, and Filtering Using FPGAs, Boston, MA, November, 1996.
• 9: J.L. Gaudiot and M. D. Ercegovae. Performance Analysis of a Data-Flow Computer with Variable Resolution Actors, Proceedings of the 4tn International Con./brence on Distributed Computing Systems, The Institute of Electrical and Electronics Engineers, Inc., Piscataway, NJ, pp. 2-9, 1984.
• 10: R. Bittner, "Development and VLSI Implementation of a High Speed Data Flow DSP Computing System," Ph.D. Dissertation, Bradley Department of Electrical and Computer Engineering, Virginia Tech, 1996, work in progress.
• 11: P. Athanas, i. Howitt, T. Rappaport, J. Reed, and B. Woerner, "A High Capacity Adaptive Wireless Receiver Implemented with a Reconfigurable Computer Architecture", ARPA GloMo Principle Investigators Conference, San Diego, CA, November 1995.
• 12: M. Bore, J. Watlington, "Cheops: A Reconfigurable Data- Flow System for Video Processing," IEEE Trans. on Circuits and Systems for Video Processing. no. 5, pp. 140-149, April 1995.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
      B.7.2 Design Aids
          Subjects: Placement and routing

General Terms:
Design, Performance

Keywords:
FPGA, VLSI, configurable computing, data flow, digital signal processing