| On tuning the microarchitecture of an HPS implementation of the VAX |
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International Symposium on Microarchitecture
archive
Proceedings of the 20th annual workshop on Microprogramming
table of contents
Colorado Springs, Colorado, United States
Pages: 162 - 167
Year of Publication: 1987
ISBN:0-89791-250-0
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Authors
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James E. Wilson
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Steve Melvin
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Michael Shebanow
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Wen-mei Hwu
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Yale N. Patt
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 9, Citation Count: 1
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ABSTRACT
The HPS Microarchitecture has been developed as an execution model for implementing various architectures at very high performance. A considerable amount of effort has gone into the use of HPS as a microarchitecture for the VAX. In this paper, we describe our first full simulation of the microVAX subset, and report the results of varying (i.e. tuning) certain important parameters.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Anderson, D. W., F. J. Sparacio, and R. M. Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling," IBM J. of R & D, vol. 11, no. 1, 1967.
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Arvind and K. P. Gostelow, "A New Interpreter for Dataflow and Its Implications for Computer Architecture," Department of Informtion and Computer Science, University of California, Irvine, Tech Report 72, October 1975.
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Hwu, W., S. Melvin, M.C. Shebanow, C. Chen, J. Wei, and Y.N.Patt, "An HPS Implementation of the VAX; Initial Design and Analysis," Proceedings of the 19th Annual Hawaii International Conference on System Sciences, 1986.
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Y. N. Patt , W. M. Hwu , M. Shebanow, HPS, a new microarchitecture: rationale and introduction, Proceedings of the 18th annual workshop on Microprogramming, p.103-108, December 03-06, 1985, Pacific Grove, California, United States
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Y. N. Patt , S. W. Melvin , W. M. Hwu , M. C. Shebanow , C. Chen, Run-time generation of HPS microinstructions from a VAX instruction stream, Proceedings of the 19th annual workshop on Microprogramming, p.75-81, October 15-17, 1986, New York, New York, United States
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Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. of R & D, vol. 11, no. 1967, pp 25 - 33.
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