A high-level microprogrammed processor

ABSTRACT

This paper presents a microprogrammable processor, intended for small real-time applications, and the development system associated with it. The processor, designed for an optimal execution of a structured high-level language, has only one level of language: a microcode allowing the execution of three operations in parallel. The possible parallelisms are detected by the compiler, which generates microcode directly. Two other tools are presented: an interactive microassembler and an interactive, window and mouse-driven, simulator. The integrated circuit for a first application is being carried out.

REFERENCES

• 1: W. Stallings, Tutorial : reduced instruction set computers, IEEE Computer Society Press, Los Alamitos, CA, 1986
• 2: Stanley Habib, Microprogramming and Firmware Engineering Methods, John Wiley & Sons, Inc., New York, NY, 1988
• 3: Niklaus Wirth, Algorithms + Data Structures = Programs, Prentice Hall PTR, Upper Saddle River, NJ, 1978
• 4: C. Iseli, A microcode compiler for the watch-oriented RISC processor, Software—Practice & Experience, v.20 n.7, p.729-747, July 1990 [doi>10.1002/spe.4380200708]
• 5: Richard Grehan , Tom Thompson , Jr.,Curtis Franklin , George A. Stewart, Introducing the new BYTE benchmarks, BYTE, v.13 n.6, p.239-266, June 1988