A framework for high-speed controller design

ABSTRACT

The SCARCE architecture framework allows the cost-effective design of application-specific architectures for a wide variety of embedded applications (controllers, signal processing, graphics). Cost-effective in this context means reduction of recurrent hardware and software development costs while achieving high performance. To aid efficient control over the design and documentation process we have integrated the framework in the ASA silicon compiler from Sagantec Inc.. The SCARCE framework is completely described by means of the Sagantec hardware description language, SID. Generating an application-specific processor reduces to a number of SID-description transformations. Currently these transformations are by hand; in the future all transformations will be made automatically. Generating the processor layout from the SID description is done by the ASA silicon compiler. To optimize the resulting layout, custom building blocks are being integrated as regular structures. Since all descriptions are in SID, the ASA silicon compiler allows simulation to take place on all stages of processor development. In this paper we describe the overall structure of the SCARCE framework, its representation in the SID description language, and the processor design trajectory.

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