An evaluation system for application specific architectures

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An evaluation system for application specific architectures

Source

International Symposium on Microarchitecture archive
Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture table of contents

Orlando, Florida, United States

Pages: 80 - 89

Year of Publication: 1990

ISBN:0-89791-413-9

Authors

Alessandro De Gloria
Paolo Faraboschi

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 4

Additional Information:

cited by collaborative colleagues

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CITED BY 4

	Alessandro De Gloria , Paolo Faraboschi, Instruction-level parallelism in Prolog: analysis and architectural support, ACM SIGARCH Computer Architecture News, v.20 n.2, p.224-233, May 1992
	Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar, An efficient technique for exploring register file size in ASIP synthesis, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Joseph A. Fisher , Paolo Faraboschi , Giuseppe Desoli, Custom-fit processors: letting applications define architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.324-335, December 02-04, 1996, Paris, France
	Bruce R. Childers , Jack W. Davidson, Custom Wide Counterflow Pipelines for High-Performance Embedded Applications, IEEE Transactions on Computers, v.53 n.2, p.141-158, February 2004

Collaborative Colleagues:

Alessandro De Gloria: colleagues

Paolo Faraboschi: colleagues

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