Instruction sets and their implementations

ABSTRACT

A view of some of the major issues facing architects and designers in the nineties is presented. For example, as processor cycles shorten the number of cycles per instruction increases, since cache/memory access time does not scale with processor speed. Thus, the kind of tradeoffs applicable in the eighties may be quite different in the nineties.

REFERENCES

• 1: Michael J. Flynn , Chad L. Mitchell , Johannes M. Mulder, And now a case for more complex instruction sets, Computer, v.20 n.9, p.71-83, Sept. 1987 [doi>10.1109/MC.1987.1663696]
• 2: Jerome C. Huck , Michael J. Flynn, Analyzing computer architectures, IEEE Press, Piscataway, NJ, 1989
• 3: Johannes M. Mulder , Nhon T. Quach , Michael J. Flynn, An area-utility model for on-chip memories and its application, Stanford University, Stanford, CA, 1990