Instruction scheduling for the Motorola 88110

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Instruction scheduling for the Motorola 88110

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International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 257 - 262

Year of Publication: 1993

ISBN:0-8186-5280-2

Authors

Mark Smotherman	Department of Computer Science, Clemson University, Clemson, SC
Shuchi Chawla	Department of Computer Science, Clemson University, Clemson, SC
Stan Cox	Department of Computer Science, Clemson University, Clemson, SC
Brian Malloy	Department of Computer Science, Clemson University, Clemson, SC

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 21, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"MC88110 Second Generation RiSC Microprocessor User's Manual," Motorola, 1991
	2	DEC Alpha Instruction Scheduler, version 1.0, Aug. 1992, FTP available from gatekeeper, dec. com.
	3	David Bernstein , Michael Rodeh, Global instruction scheduling for superscalar machines, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.241-255, June 24-28, 1991, Toronto, Ontario, Canada
	4	David Bernstein , Doron Cohen , Hugo Krawczyk, Code duplication: an assist for global instruction scheduling, Proceedings of the 24th annual international symposium on Microarchitecture, p.103-113, September 1991, Albuquerque, New Mexico, Puerto Rico [doi>10.1145/123465.123486]
	5	David Bernstein , Doron Cohen , Yuval Lavon , Vladimir Rainish, Performance evaluation of instruction scheduling on the IBM RISC System/6000, Proceedings of the 25th annual international symposium on Microarchitecture, p.226-235, December 01-04, 1992, Portland, Oregon, United States
	6	David G. Bradlee , Susan J. Eggers , Robert R. Henry, Integrating register allocation and instruction scheduling for RISCs, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.122-131, April 08-11, 1991, Santa Clara, California, United States
	7	S. Cox, "Code Scheduling for the MC88110 Superscalar RISC Processor Using Reservation Tables," M.S. Paper, Dept. of Computer Science, Clemson Univ., Dec. 1992.
	8	Keith Diefendorff , Michael Allen, The Motorola 88110 superscalar RISC microprocessor, Proceedings of the thirty-seventh international conference on COMPCON, p.157-162, January 1992, San Francisco, California, United States
	9	Keith Diefendorff , Michael Allen, Organization of the Motorola 88110 Superscalar RISC Microprocessor, IEEE Micro, v.12 n.2, p.40-63, March 1992 [doi>10.1109/40.127582]
	10	J. Fisher, "Trace Scheduling, A Technique for Global Microcode Compaction," IEEE Trans. Computers, July 1981, pp. 478-490.
	11	Sanjay M. Krishamurthy, A brief survey of papers on scheduling for pipelined processors, ACM SIGPLAN Notices, v.25 n.7, p.97-106, July 1990 [doi>10.1145/382076.382650]
	12	Alexandru Nicolau, Percolation Scheduling: A Parallel Compilation Technique, Cornell University, Ithaca, NY, 1985
	13	Michael J. Phillip, Performance issues for the 88110 RISC microprocessor, Proceedings of the thirty-seventh international conference on COMPCON, p.163-168, January 1992, San Francisco, California, United States
	14	Mark Smotherman , Sanjay Krishnamurthy , P. S. Aravind , David Hunnicutt, Efficient DAG construction and heuristic calculation for instruction scheduling, Proceedings of the 24th annual international symposium on Microarchitecture, p.93-102, September 1991, Albuquerque, New Mexico, Puerto Rico [doi>10.1145/123465.123482]
	15	Jack Walicki , John D. Laughlin, Operation scheduling in reconfigurable, multifunction pipelines, Proceedings of the 20th annual workshop on Microprogramming, p.80-87, December 01-04, 1987, Colorado Springs, Colorado, United States [doi>10.1145/255305.255319]
	16	H. S. Warren, Jr., Instruction scheduling for the IBM RISC System/6000 processor, IBM Journal of Research and Development, v.34 n.1, p.85-92, Jan. 1990
	17	Graham Wood, Global optimization of microprograms through modular control constructs, Proceedings of the 12th annual workshop on Microprogramming, p.1-6, November 18-21, 1979, Hershey, Pennslyvania, United States

CITED BY 2

	Thomas M. Conte , Kishore N. Menezes , Patrick M. Mills , Burzin A. Patel, Optimization of instruction fetch mechanisms for high issue rates, ACM SIGARCH Computer Architecture News, v.23 n.2, p.333-344, May 1995
	Raymond Lo , Sun Chan , Fred Chow , Shin-Ming Liu, Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution, Proceedings of the 27th annual international symposium on Microarchitecture, p.148-152, November 30-December 02, 1994, San Jose, California, United States

INDEX TERMS

Keywords:
MC88110, cache alignment, instruction scheduling, superscalar processors

Collaborative Colleagues:

Mark Smotherman: colleagues

Shuchi Chawla: colleagues

Stan Cox: colleagues

Brian Malloy: colleagues

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