An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors

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An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors

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International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 236 - 246

Year of Publication: 1993

ISBN:0-8186-5280-2

Authors

Ing-Jer Huang	Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California
Alvin M. Despain	Advanced Computer Architecture Laboratory, Department of Electrical Engineering - Systems, University of Southern California

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 15, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mauricio Breternitz, Jr. , John Paul Shen, Architecture synthesis of high-performance application-specific processors, Proceedings of the 27th ACM/IEEE conference on Design automation, p.542-548, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123398]
	2	Richard J. Cloutier , Donald E. Thomas, Synthesis of pipelined instruction set processors, Proceedings of the 30th international conference on Design automation, p.583-588, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165053]
	3	John L. Hennessy , Thomas Gross, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages and Systems (TOPLAS), v.5 n.3, p.422-448, July 1983 [doi>10.1145/2166.357217]
	4	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	5	I.-J. Huang , A. M. Despain, High level synthesis of pipelined instruction set processors and back-end compilers, Proceedings of the 29th ACM/IEEE conference on Design automation, p.135-140, June 08-12, 1992, Anaheim, California, United States
	6	Ing-Jer Huang , Alvin M. Despain, Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.594-599, November 07-11, 1993, Santa Clara, California, United States
	7	Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation, p.764-769, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127766]
	8	Gerry Kane, MIPS RISC architecture, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
	9	Robert M. Keller, Look-Ahead Processors, ACM Computing Surveys (CSUR), v.7 n.4, p.177-195, Dec. 1975 [doi>10.1145/356654.356657]
	10	Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, 1991
	11	Peter M. Kogge, The Architecture of Pipelined Computers, MacGraw-HiH, 1981
	12	Janak H. Patel , Edward S. Davidson, Improving the throughput of a pipeline by insertion of delays, Proceedings of the 3rd annual symposium on Computer architecture, p.159-164, January 19-21, 1976
	13	C.-Y. Tsui , H.-T. Chen , G. Cheng , S. Liu , S. Wu , A. M. Despain , I. Pyo , C. L. Su , I.-J. Huang , K.-R. Pan , Y.-S. Koh, Application-driven design automation for microprocessor design, Proceedings of the 29th ACM/IEEE conference on Design automation, p.512-517, June 08-12, 1992, Anaheim, California, United States
	14	Apoorv Srivastava , Alvin M. Despain, Prophetic branches: a branch architecture for code compaction and efficient execution, Proceedings of the 26th annual international symposium on Microarchitecture, p.94-99, December 01-03, 1993, Austin, Texas, United States
	15	R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM J. Res. Dev., January 1967, pp. 25-33.
	16	Programming Manual for the Teledyne TDY-43 Computer, Teledyne Systems Company, 1988

CITED BY

Pritpal S. Ahuja , Douglas W. Clark , Anne Rogers, The performance impact of incomplete bypassing in processor pipelines, Proceedings of the 28th annual international symposium on Microarchitecture, p.36-45, November 29-December 01, 1995, Ann Arbor, Michigan, United States

INDEX TERMS

Keywords:
compiler back-end generation, hardware/software tradeoffs, high level synthesis, inter-instruction dependency, pipeline hazard resolution

Collaborative Colleagues:

Ing-Jer Huang: colleagues

Alvin M. Despain: colleagues

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