Register renaming and dynamic speculation

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Register renaming and dynamic speculation: an alternative approach

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International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 202 - 213

Year of Publication: 1993

ISBN:0-8186-5280-2

Authors

Mayan Moudgill	Department of Computer Science, Cornell University, Ithaca, NY
Keshav Pingali	Department of Computer Science, Cornell University, Ithaca, NY
Stamatis Vassiliadis	School of Electrical Engineering, Cornell University, Ithaca, NY and IBM Corporation, Enterprise Systems, Poughkeepsie, NY

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 16, Downloads (12 Months): 49, Citation Count: 33

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	8	Mayan Moudgill , Keshav Pingali , Stamatis Vassiliadis, Register Renaming and Dynamic Speculation: an Alternative Approach, Cornell University, Ithaca, NY, 1993
	9	Val Popescu , Merle Schultz , John Spracklen , Gary Gibson , Bruce Lightner , David Isaman, The Metaflow Architecture, IEEE Micro, v.11 n.3, p.10-13, 63-73, May 1991 [doi>10.1109/40.87564]
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	13	S. Vassiliadis , B. Blaner , R. J. Eickemeyer, SCISM: a scalable compound instruction set machine, IBM Journal of Research and Development, v.38 n.1, p.59-78, Jan. 1994
	14	David W. Wall, Limits of instruction-level parallelism, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.176-188, April 08-11, 1991, Santa Clara, California, United States

CITED BY 33

	Matthew Postiff , David Greene , Steven Raasch , Trevor Mudge, Integrating superscalar processor components to implement register caching, Proceedings of the 15th international conference on Supercomputing, p.348-357, June 2001, Sorrento, Italy
	Daniel Ortega , Mateo Valero , Eduard Ayguadé, A novel renaming mechanism that boosts software prefetching, Proceedings of the 15th international conference on Supercomputing, p.501-510, June 2001, Sorrento, Italy
	Stephen Jourdan , Ronny Ronen , Michael Bekerman , Bishara Shomar , Adi Yoaz, A novel renaming scheme to exploit value temporal locality through physical register reuse and unification, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.216-225, November 1998, Dallas, Texas, United States
	Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Dynamically allocating processor resources between nearby and distant ILP, ACM SIGARCH Computer Architecture News, v.29 n.2, p.26-37, May 2001
	Renju Thomas , Manoj Franklin , Chris Wilkerson , Jared Stark, Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Dmitry Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose, Isolating Short-Lived Operands for Energy Reduction, IEEE Transactions on Computers, v.53 n.6, p.697-709, June 2004
	Adrián Cristal , José F. Martínez , Josep Llosa , Mateo Valero, A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, v.32 n.3, p.3-10, June 2004
	Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan, An analysis of a resource efficient checkpoint architecture, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.4, p.418-444, December 2004
	Srikanth T. Srinivasan , Ravi Rajwar , Haitham Akkary , Amit Gandhi , Mike Upton, Continual flow pipelines, ACM SIGOPS Operating Systems Review, v.38 n.5, December 2004
	Adrián Cristal , Oliverio J. Santana , Mateo Valero , José F. Martínez, Toward kilo-instruction processors, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.4, p.389-417, December 2004
	Srikanth T. Srinivasan , Ravi Rajwar , Haitham Akkary , Amit Gandhi , Michael Upton, Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance, IEEE Micro, v.24 n.6, p.62-73, November 2004
	Teresa Monreal , Victor Vinals , Jose Gonzalez , Antonio Gonzalez , Mateo Valero, Late Allocation and Early Release of Physical Registers, IEEE Transactions on Computers, v.53 n.10, p.1244-1259, October 2004
	R. González , A. Cristal , M. Pericas , M. Valero , A. Veidenbaum, An asymmetric clustered processor based on value content, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
	Daniel Ortega , Mateo Valero , Eduard Ayguadé, Dynamic memory instruction bypassing, International Journal of Parallel Programming, v.32 n.3, p.199-224, June 2004
	Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Reducing the complexity of the register file in dynamic superscalar processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	José F. Martínez , Jose Renau , Michael C. Huang , Milos Prvulovic , Josep Torrellas, Cherry: checkpointed early resource recycling in out-of-order microprocessors, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
	Jesús Alastruey , Teresa Monreal , Víctor Viñals , Mateo Valero, Speculative early register release, Proceedings of the 3rd conference on Computing frontiers, May 03-05, 2006, Ischia, Italy
	Rama Sangireddy, Register port complexity reduction in wide-issue processors with selective instruction execution, Microprocessors & Microsystems, v.31 n.1, p.51-62, February, 2007
	Engin Ipek , Meyrem Kirman , Nevin Kirman , Jose F. Martinez, Core fusion: accommodating software diversity in chip multiprocessors, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	Deniz Balkan , Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose, SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
	Ahmed S. Al-Zawawi , Vimal K. Reddy , Eric Rotenberg , Haitham H. Akkary, Transparent control independence (TCI), ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
	David W. Oehmke , Nathan L. Binkert , Trevor Mudge , Steven K. Reinhardt, How to Fake 1000 Registers, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.7-18, November 12-16, 2005, Barcelona, Spain
	Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi, Physical Register Inlining, ACM SIGARCH Computer Architecture News, v.32 n.2, p.325, March 2004
	Gonzalez Gonzalez , Adrian Cristal , Daniel Ortega , Alexander Veidenbaum , Mateo Valero, A Content Aware Integer Register File Organization, ACM SIGARCH Computer Architecture News, v.32 n.2, p.314, March 2004
	Brian Fahs , Todd Rafacz , Sanjay J. Patel , Steven S. Lumetta, Continuous Optimization, ACM SIGARCH Computer Architecture News, v.33 n.2, p.86-97, May 2005
	Akihiro Yamamoto , Yusuke Tanaka , Hideki Ando , Toshio Shimada, Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation, Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, p.33-40, September 16-16, 2007, Brasov, Romania
	Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan, Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.423, December 03-05, 2003
	Amit Golander , Shlomo Weiss, Hiding the misprediction penalty of a resource-efficient high-performance processor, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.4, p.1-32, January 2008
	Teresa Monreal , Víctor Vinals , Antonio Gonzalez , Mateo Valero, Hardware support for early register release, International Journal of High Performance Computing and Networking, v.3 n.2/3, p.83-94, November 2005
	Adrian Cristal , Josep Llosa , Mateo Valero , Daniel Ortega, Future ILP processors, International Journal of High Performance Computing and Networking, v.2 n.1, p.1-10, March 2004
	Deniz Balkan , Joseph Sharkey , Dmitry V. Ponomarev , Kanad Ghose, Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption, IEEE Transactions on Computers, v.57 n.1, p.82-95, January 2008
	Isidro Gonzalez , Marco Galluzzi , Alex Veidenbaum , Marco A. Ramirez , Adrian Cristal , Mateo Valero, A distributed processor state management architecture for large-window processors, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.11-22, November 08-12, 2008

Collaborative Colleagues:

Mayan Moudgill: colleagues

Keshav Pingali: colleagues

Stamatis Vassiliadis: colleagues

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