An analysis of dynamic scheduling techniques for symbolic applications

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An analysis of dynamic scheduling techniques for symbolic applications

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International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 185 - 191

Year of Publication: 1993

ISBN:0-8186-5280-2

Authors

Alessandra Costa	University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Alessandro De Gloria	University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Paolo Faraboschi	University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy
Mauro Olivieri	University of Genoa - DIBE, Via Opera Pia 11a, 16145 Genova, Italy

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, Proceedings of the 18th annual international symposium on Computer architecture, p.276-286, May 27-30, 1991, Toronto, Ontario, Canada
	2	Alessandro De Gloria , Paolo Faraboschi, Instruction-level parallelism in Prolog: analysis and architectural support, Proceedings of the 19th annual international symposium on Computer architecture, p.224-233, May 19-21, 1992, Queensland, Australia
	3	J. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Trans. Comput., C-30(7):478-490, July 1981.
	4	Joseph A. Fisher, Very Long Instruction Word architectures and the ELI-512, Proceedings of the 10th annual international symposium on Computer architecture, p.140-150, June 13-17, 1983, Stockholm, Sweden
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	7	M. Johnson. Superscalar Design. Prentice Hall, Eng\|ewood Cliffs, N J) 1990.
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	10	A. Nicolau and J. Fisher. Measuring the parallelism available for very long instruction word architectures. IEEE Trans. Comput., C-33(11):968-976, Nov. 1984.
	11	B. Ramakrishna Rau , Christopher D. Glaeser , Raymond L. Picard, Efficient code generation for horizontal architectures: Compiler techniques and architectural support, Proceedings of the 9th annual symposium on Computer Architecture, p.131-139, April 26-29, 1982, Austin, Texas, United States
	12	M. D. Smith , M. Johnson , M. A. Horowitz, Limits on multiple instruction issue, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.290-302, April 03-06, 1989, Boston, Massachusetts, United States
	13	Peter Lodewijk Van Roy, Can logic programming execute as fast as imperative programming?, University of California at Berkeley, Berkeley, CA, 1991
	14	David W. Wall, Limits of instruction-level parallelism, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.176-188, April 08-11, 1991, Santa Clara, California, United States

Collaborative Colleagues:

Alessandra Costa: colleagues

Alessandro De Gloria: colleagues

Paolo Faraboschi: colleagues

Mauro Olivieri: colleagues

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