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Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors
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Source International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents
Austin, Texas, United States
Pages: 164 - 175  
Year of Publication: 1993
ISBN:0-8186-5280-2
Authors
Tse-Yu Yeh  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Yale N. Patt  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Sponsors
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 18,   Citation Count: 4
Additional Information:

references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
2
Brian K. Bray , M. J. Flynn, Strategies for branch target buffers, Proceedings of the 24th annual international symposium on Microarchitecture, p.42-50, September 1991, Albuquerque, New Mexico, Puerto Rico  [doi>10.1145/123465.123473]
3
Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, Proceedings of the 18th annual international symposium on Computer architecture, p.276-286, May 27-30, 1991, Toronto, Ontario, Canada
4
Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada
 
5
Intel Corporation, "PentiumTM Processor User's Manual, Volume 1, 2, and 3', Mt. Prospect, Illinois, 1993.
6
David R. Kaeli , Philip G. Emma, Branch history table prediction of moving target branches due to subroutine returns, Proceedings of the 18th annual international symposium on Computer architecture, p.34-42, May 27-30, 1991, Toronto, Ontario, Canada
 
7
J. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design", IEEE Computer, pp. 6-22, Jan. 1984.
 
8
J. S. Liptay, Design of the IBM Enterprise System/9000 high-end processor, IBM Journal of Research and Development, v.36 n.4, p.713-731, July 1992
 
9
Motorola Inc., "M88100 User's Manual", Phoenix, Arizona, March 13, 1989.
 
10
James E. Smith, A study of branch prediction strategies, Proceedings of the 8th annual symposium on Computer Architecture, p.135-148, May 12-14, 1981, Minneapolis, Minnesota, United States
11
Tse-Yu Yeh , Yale N. Patt, Alternative implementations of two-level adaptive branch prediction, Proceedings of the 19th annual international symposium on Computer architecture, p.124-134, May 19-21, 1992, Queensland, Australia
12
Tse-Yu Yeh , Yale N. Patt, A comprehensive instruction fetch mechanism for a processor supporting speculative execution, Proceedings of the 25th annual international symposium on Microarchitecture, p.129-139, December 01-04, 1992, Portland, Oregon, United States
13
Tse-Yu Yeh , Yale N. Patt, A comparison of dynamic branch predictors that use two levels of branch history, Proceedings of the 20th annual international symposium on Computer architecture, p.257-266, May 16-19, 1993, San Diego, California, United States
14
Tse-Yu Yeh , Deborah T. Marr , Yale N. Patt, Increasing the instruction fetch rate via multiple branch prediction and a branch address cache, Proceedings of the 7th international conference on Supercomputing, p.67-76, July 19-23, 1993, Tokyo, Japan  [doi>10.1145/165939.165956]

CITED BY  4
Pierre Michaud , André Seznec , Stéphan Jourdan, An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors, International Journal of Parallel Programming, v.29 n.1, p.35-58, February 2001
Shu-Lin Hwang , Feipei Lai, Two cache lines prediction for a wide-issue micro-architecture, Australian Computer Science Communications, v.23 n.4, p.71-79, January 2001
Dan Tsafrir , Yoav Etsion , Dror G. Feitelson, Secretly monopolizing the CPU without superuser privileges, Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium, p.1-18, August 06-10, 2007, Boston, MA
Ioana Burcea , Andreas Moshovos, Phantom-BTB: a virtualized branch target buffer design, ACM SIGPLAN Notices, v.44 n.3, March 2009
Collaborative Colleagues:
Tse-Yu Yeh: colleagues
Yale N. Patt: colleagues

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