A study on the number of memory ports in multiple instruction issue machines

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A study on the number of memory ports in multiple instruction issue machines

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International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 49 - 59

Year of Publication: 1993

ISBN:0-8186-5280-2

Authors

Soo-Mook Moon	IBM T.J. Watson Research Center, Hewlett-Packard Company, 11000 Wolfe Road, MS42U5, Cupertino, CA
Kemal Ebcioğlu	IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 18, Citation Count: 7

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Soo-Mook Moon , Kemal Ebcioğlu, An efficient resource-constrained global scheduling technique for superscalar and VLIW processors, Proceedings of the 25th annual international symposium on Microarchitecture, p.55-71, December 01-04, 1992, Portland, Oregon, United States
	2	David Bernstein , Michael Rodeh, Global instruction scheduling for superscalar machines, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.241-255, June 24-28, 1991, Toronto, Ontario, Canada
	3	Scott A. Mahlke , David C. Lin , William Y. Chen , Richard E. Hank , Roger A. Bringmann, Effective compiler support for predicated execution using the hyperblock, Proceedings of the 25th annual international symposium on Microarchitecture, p.45-54, December 01-04, 1992, Portland, Oregon, United States
	4	A. Aiken , A. Nicolau, A Development Environment for Horizontal Microcode, IEEE Transactions on Software Engineering, v.14 n.5, p.584-594, May 1988 [doi>10.1109/32.6136]
	5	Y. N. Patt , W. M. Hwu , M. Shebanow, HPS, a new microarchitecture: rationale and introduction, Proceedings of the 18th annual workshop on Microprogramming, p.103-108, December 03-06, 1985, Pacific Grove, California, United States
	6	Gurindar S. Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, v.39 n.3, p.349-359, March 1990 [doi>10.1109/12.48865]
	7	Michael D. Smith , Mark Horowitz , Monica S. Lam, Efficient superscalar performance through boosting, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, p.248-259, October 12-15, 1992, Boston, Massachusetts, United States
	8	Stephen Melvin , Yale Patt, Exploiting fine-grained parallelism through a combination of hardware and software techniques, Proceedings of the 18th annual international symposium on Computer architecture, p.287-296, May 27-30, 1991, Toronto, Ontario, Canada
	9	David W. Wall, Limits of instruction-level parallelism, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.176-188, April 08-11, 1991, Santa Clara, California, United States
	10	Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, Proceedings of the 18th annual international symposium on Computer architecture, p.276-286, May 27-30, 1991, Toronto, Ontario, Canada
	11	Monica S. Lam , Robert P. Wilson, Limits of control flow on parallelism, Proceedings of the 19th annual international symposium on Computer architecture, p.46-57, May 19-21, 1992, Queensland, Australia
	12	Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada
	13	S.-M. Moon and K. Ebcio~lu. On Performance and Efficiency of VLIW and Superscalar. In Proceedings of 1993 International Conference on Parallel Processing, pages 2:283-287, Aug 1993.
	14	Gurindar S. Sohi , Manoj Franklin, High-bandwidth data memory systems for superscalar processors, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.53-62, April 08-11, 1991, Santa Clara, California, United States
	15	K. Ebcio~lu. Some Design Ideas for a VLIW Architecture for Sequential Natured Software. In M. Cosnard et al., editor, Parallel Processing(proceedings of IFIP WG 10.3 Working Conference on Parallel Processing (Piss, italy), pages 3-21. North Holland, April 1988.
	16	S.-M. Moon. Increasing Instruction-Level Parallelism through Multi-way Branching. In Proceedings of 1993 International Uonference on Parallel Processing, pages 2:241-245, Aug 1993.
	17	Toshio Nakatani , Kemal Ebcioğlu, Using a lookahead window in a compaction-based parallelizing compiler, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.57-68, November 27-29, 1990, Orlando, Florida, United States
	18	T. Nakatani , K. Ebcioğlu, “Combining” as a compilation technique for VLIW architectures, Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture, p.43-55, August 14-16, 1989, Dublin, Ireland
	19	Soo-Mook Moon , Kemal Ebcioglu , Ashok K. Agrawala, Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, p.229-242, January 20-22, 1993
	20	K. Ebcioğlu , Toshio Nakatani, A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture, Selected papers of the second workshop on Languages and compilers for parallel computing, p.213-229, May 1990, Urbana, Illinois, United States
	21	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	22	Gabriel M. Silberman , Kemal Ebcioğlu, An architectural framework for migration from CISC to higher performance platforms, Proceedings of the 6th international conference on Supercomputing, p.198-215, July 19-24, 1992, Washington, D. C., United States [doi>10.1145/143369.143410]
	23	John R. Ellis, Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific), 1985
	24	H. Warren, M. Auslander, G. Chaitin, A. Chibib M. Hopkins, and A. MacKay. Final Code Generation in the PL.8 Compiler. Researdl Report RC 11974, IBM Research Division, T.J. Watson Research Center, fun 1986.
	25	IBM. A Special Issue on IBM RISC System/6000. IBM Journal of Research and Development, 34(1), Jan 1990.
	26	Soo-Mook Moon , Scott D. Carson , Ashok K. Agrawala, Hardware implementation of a general multi-way jump mechanism, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.38-45, November 27-29, 1990, Orlando, Florida, United States
	27	Anne Rogers , Kai Li, Software support for speculative loads, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, p.38-50, October 12-15, 1992, Boston, Massachusetts, United States

CITED BY 7

	Soo-Mook Moon , Kemal Ebcioğlu, Parallelizing nonnumerical code with selective scheduling and software pipelining, ACM Transactions on Programming Languages and Systems (TOPLAS), v.19 n.6, p.853-898, Nov. 1997
	Bogong Su , Stanley Habib , Wei Zhao , Jian Wang , Youfeng Wu, A study of pointer aliasing for software pipelining using run-time disambiguation, Proceedings of the 27th annual international symposium on Microarchitecture, p.112-117, November 30-December 02, 1994, San Jose, California, United States
	J. Ph. Diguet , S. Wuytack , F. Catthoor , H. De Man, Formalized methodology for data reuse exploration in hierarchical memory mappings, Proceedings of the 1997 international symposium on Low power electronics and design, p.30-35, August 18-20, 1997, Monterey, California, United States
	Kenneth M. Wilson , Kunle Olukotun, High Bandwidth On-Chip Cache Design, IEEE Transactions on Computers, v.50 n.4, p.292-307, April 2001
	Soo-Mook Moon, Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.294-297, June 27-29, 1995, Limassol, Cyprus
	Lode Nachtergaele , Toon Gijbels , Jan Bormans , Francky Catthoor , Ivo Bolsens, Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors, Journal of VLSI Signal Processing Systems, v.27 n.1-2, p.161-169, Feb. 2001
	Wolfram Amme , Peter Braun , François Thomasset , Eberhard Zehendner, Data Dependence Analysis of Assembly Code, International Journal of Parallel Programming, v.28 n.5, p.431-467, Oct. 2000

INDEX TERMS

Keywords:
ILP, memory disambiguation, memory ports, speculative loads, static scheduling

Collaborative Colleagues:

Soo-Mook Moon: colleagues

Kemal Ebcioğlu: colleagues

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