Two-ported cache alternatives for superscalar processors

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Two-ported cache alternatives for superscalar processors

Full text

Pdf (1.01 MB)

Source

International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 41 - 48

Year of Publication: 1993

ISBN:0-8186-5280-2

Authors

Andrew Wolfe	Department of Electrical Engineering, Princeton University
Rodney Boleyn	Department of Electrical Engineering, Princeton University

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 2, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H.B. Bakoglu, et al., "iBM Second-Generation RI$C Machine Organization," ICCD '89,138-142, IEEE, 1989.
	2	Greg Blanck , Steve Krueger, The SuperSPARC microprocessor, Proceedings of the thirty-seventh international conference on COMPCON, p.136-141, January 1992, San Francisco, California, United States
	3	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	4	Tse-Yu Yeh , Yale N. Patt, Two-level adaptive training branch prediction, Proceedings of the 24th annual international symposium on Microarchitecture, p.51-61, September 1991, Albuquerque, New Mexico, Puerto Rico [doi>10.1145/123465.123475]
	5	B. Case, "DEC's Alpha Architecture Premiers", Microprocessor Report, v. 6, n. 3, March 1992.
	6	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
	7	Thomas M. Conte, Tradeoffs in processor/memory interfaces for superscalar processors, Proceedings of the 25th annual international symposium on Microarchitecture, p.202-205, December 01-04, 1992, Portland, Oregon, United States
	8	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	9	R. Boleyn J. Duiugiugi9u iyu}guiy}g iugiu uig Wolfe, "A Split Data Cache for Superscalar Processor.~", in ICCD '93, Oct_. 1993.
	10	Gurindar S. Sohi , Manoj Franklin, High-bandwidth data memory systems for superscalar processors, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.53-62, April 08-11, 1991, Santa Clara, California, United States
	11	Mike Johnson, Superscalar Microprocessor Design, Prentice Hall, Englewood Cliffs, NJ, 1991.
	12	PentiumTM Processor User's Manual, Intel, 1993.
	13	L. Gwennap, "SGI Provides Overview of TFP CPU", Microprocessor Report, v. 7, n. 2, Feb. 15 1~/f93.
	14	R. Boleyn and A. Wolfe, "Experimental Measurement of Two-ported Caches for Superscalar Processors", Princeton University Computer Engineering Technical Report CE-A93-3, August 1993.

CITED BY 2

	Paul Racunas , Yale N. Patt, Partitioned first-level cache design for clustered microarchitectures, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
	Soo-Mook Moon, Increasing cache bandwidth using multi-port caches for exploiting ILP in non-numerical code, Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, p.294-297, June 27-29, 1995, Limassol, Cyprus

Collaborative Colleagues:

Andrew Wolfe: colleagues

Rodney Boleyn: colleagues

Adobe Acrobat

QuickTime

Windows Media Player

Real Player