Employing finite automata for resource scheduling

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Employing finite automata for resource scheduling

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International Symposium on Microarchitecture archive
Proceedings of the 26th annual international symposium on Microarchitecture table of contents

Austin, Texas, United States

Pages: 12 - 20

Year of Publication: 1993

ISBN:0-8186-5280-2

Author

Thomas Müller

GMD Forschungsstelle an der Universität Karlsruhe, Vincenz-Prieβnitz-Str. 1, D-76131 Karlsruhe, Germany

Sponsors

IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 19, Citation Count: 10

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	2	Alfred V. Aho , John E. Hopcroft, The Design and Analysis of Computer Algorithms, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1974
	3	David Gordon Bradlee. Retargelable Instruction Scheduling for Pipelined Processors. PhD thesis, Department of Computer Science and Engineering, University of Washington, Seattle, 1991.
	4	H. Emmelmann , F.-W. Schröer , L. Landwehr, BEG: a generation for efficient back ends, Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation, p.227-237, June 19-23, 1989, Portland, Oregon, United States
	5	M. Anton Ertl , Andreas Krall, Instruction Scheduling for Complex Pipelines, Proceedings of the 4th International Conference on Compiler Construction, p.207-218, October 05-07, 1992
	6	Joseph A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, c-30(7):478-490, jul 1981.
	7	Christopher W. Fraser , Robert R. Henry, Hard-coding bottom-up code generation tables to save time and space, Software—Practice & Experience, v.21 n.1, p.1-12, Jan. 1991 [doi>10.1002/spe.4380210102]
	8	John E. Hopcroft , Jeffrey D. Ullman, Introduction To Automata Theory, Languages, And Computation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
	9	Gerry Kane. MIPS R2000 RISC Architecture. Prentice-Hall, 1988.
	10	M. Lam, Software pipelining: an effective scheduling technique for VLIW machines, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.318-328, June 20-24, 1988, Atlanta, Georgia, United States
	11	D. Liu , W. K. Giloi, A loop optimization technique based on scheduling table, Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture, p.135-140, August 14-16, 1989, Dublin, Ireland

CITED BY 10

	R. Govindarajan , N. S. S. Narasimha Rao , E. R. Altman , Guang R. Gao, Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory, International Journal of Parallel Programming, v.28 n.1, p.1-46, February 2000
	John C. Gyllenhaal , Wen-Mei W. Hwu , B. Ramakrishna Rau, Optimization of Machine Descriptions for Efficient Use, International Journal of Parallel Programming, v.26 n.4, p.417-447, August 1998
	John C. Gyllenhaal , Wen-mei W. Hwu , B. Ramabriohna Rau, Optimization of machine descriptions for efficient use, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.349-358, December 02-04, 1996, Paris, France
	Alexandre E. Eichenberger , Edward S. Davidson, A reduced multipipeline machine description that preserves scheduling constraints, ACM SIGPLAN Notices, v.31 n.5, p.12-22, May 1996
	Todd A. Proebsting , Christopher W. Fraser, Detecting pipeline structural hazards quickly, Proceedings of the 21st ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.280-286, January 16-19, 1994, Portland, Oregon, United States
	Vasanth Bala , Norman Rubin, Efficient instruction scheduling using finite state automata, Proceedings of the 28th annual international symposium on Microarchitecture, p.46-56, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	V. Janaki Ramanan , R. Govindarajan, Resource usage models for instruction scheduling: two new models and a classification, Proceedings of the 13th international conference on Supercomputing, p.417-424, June 20-25, 1999, Rhodes, Greece
	Mark W. Bailey , Jack W. Davidson, A formal model and specification language for procedure calling conventions, Proceedings of the 22nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.298-310, January 23-25, 1995, San Francisco, California, United States
	Mark W. Bailey , Jack W. Davidson, Automatic Detection and Diagnosis of Faults in Generated Code for Procedure Calls, IEEE Transactions on Software Engineering, v.29 n.11, p.1031-1042, November 2003
	Christopher W. Milner , Jack W. Davidson, Quick piping: a fast, high-level model for describing processor pipelines, ACM SIGPLAN Notices, v.37 n.7, July 2002

Collaborative Colleagues:

Thomas Müller: colleagues

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