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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M.Harrand, M.Henry, RChaisemartin, RMougeat, Y.Durand, A.Tournier, R.Wilson, J.Herluison, J.Langchambon, J.Bauer, M.Runtz and J.Bulone, "A single chip videophone encoder/decoder", Proc. IEEE Int. Solid-State Cilv. Conf., pp.292-293, Feb. 1995.
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K.Ishihara et al. "A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search", Proc. IEEE Int. Solid-State City. Conf., pp.288-289, Feb. 1995.
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Martin Janssen , Francky Catthoor , Hugo De Man, A specification invariant technique for operation cost minimisation in flow-graphs, Proceedings of the 7th international symposium on High-level synthesis, p.146-151, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
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Y. Jehng, L. Chen, T. Chiueh, "An efficient and simple VLSI tree architecture for motion estimation algorithms", IEEE Transactions on Signal Processing, vol. 41, pp. 889-900,Feb. 1993.
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T. Komarek, P. Pirsch, "Array Architectures for Block Matching Algorithms", IEEE Transactions on Circuits and Systems, vo136, Oct. 1989.
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T.H.Meng, B.Gordon, E.Tsern, A.Hung, "Portable video-on-demandin wireless communication", special issue on "Low power design" of the Proceedings of the IEEE, Vol.83, No.4, pp.659-680, April 1995.
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T.Miyazaki, I.Kuroda, and M.Imanishi, "A low-cost MPEG1 video encoder based on a single chip DSP", Proc. DSPX, pp.136-142,1994.
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L. Nachtergaele , F. Catthoor , F. Balasa , F. Franssen , E. De Greef , H. Samsom , H. De Man, Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems, Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing, p.82, August 07-08, 1995
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J.Rosseel, F.Catthoor, H.De Man, "The systematic design of a motion estimation array architecture", P~vc. Intnl. Conf. on Applic.-Spec.Array P~vcessors, Barcelona, Spain, pp.40-54, Sep.91.
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T.Seki, E.Itoh, C.Furukawa, I.Maeno, T.Ozawa, H.Sano, N.Suzuki, "A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier",IEEE Journal of Solid- State Ci~vuits, Vol.28, No.4, pp.478-483, Apr. 1993.
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D.Singh, J.Rabaey, M.Pedram, ECatthoor, S.Rajgopal, N.Sehgal, T.Mozdzen, "Power conscious CAD tools and methodologies: a perspective", special issue on "Low power design" of the Proceedings of the IEEE, Vol.83, No.4, pp.570-594, April 1995.
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M.Toyokura et al., "A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 codec", IEEE J. Solidstate City., Vol.SC-29, pp. 1474-1480, Dec. 1994.
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RVan Oostende, G.Van Wauwe, "Low power design: a gated-clock strategy", Low Power Workshop, Ulm, Germany, Sep. 1994.
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S.Wuytack, ECatthoor, F.Franssen, L.Nachtergaele, H.De Man, "Global communication and memory optimizing transformations for low power systems", IEEE Intnl. Workshop on Low Power Design, Napa CA, pp.203-208, April 1994.
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CITED BY 17
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J. Ph. Diguet , S. Wuytack , F. Catthoor , H. De Man, Formalized methodology for data reuse exploration in hierarchical memory mappings, Proceedings of the 1997 international symposium on Low power electronics and design, p.30-35, August 18-20, 1997, Monterey, California, United States
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K. Masselos , K. Danckaert , F. Catthoor , N. Zervas , C. E. Goutis , H. De Man, A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints, Journal of VLSI Signal Processing Systems, v.26 n.3, p.291-317, Nov. 2000
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Russell Tessier , Vaughn Betz , David Neto , Thiagaraja Gopalsamy, Power-aware RAM mapping for FPGA embedded memory blocks, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
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Koen Danckaert , Francky Catthoor , Hugo De Man, A preprocessing step for global loop transformations for data transfer optimization, Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems, p.34-40, November 17-19, 2000, San Jose, California, United States
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