| Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer |
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International Symposium on Low Power Electronics and Design
archive
Proceedings of the 1996 international symposium on Low power electronics and design
table of contents
Monterey, California, United States
Pages: 353 - 358
Year of Publication: 1996
ISBN:0-7803-3571-6
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Authors
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M. Hiraki
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Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan
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R. Bajwa
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Semiconductor Research Laboratory, Hitachi America, Ltd., San Jose, CA
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H. Kojima
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Semiconductor Research Laboratory, Hitachi America, Ltd., San Jose, CA
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D. Gorny
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Semiconductor Research Laboratory, Hitachi America, Ltd., San Jose, CA
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K. Nitta
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Semiconductor and Integerated Circuits Division, Hitachi, Ltd., Kodaria, Tokyo 187, Japan
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A. Shridhar
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Semiconductor Research Laboratory, Hitachi America, Ltd., San Jose, CA
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K. Sasaki
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Semiconductor Research Laboratory, Hitachi America, Ltd., San Jose, CA
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K. Seki
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Central Research Laboratory, Hitachi, Ltd., Kokubunji, Tokyo 185, Japan
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| Sponsors |
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IEEE Press
Piscataway, NJ, USA
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| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 5
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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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H. Sasaki, "Multimedia Complex on a Chip," in ISSCC Dig. Tech. Papers, pp. 16-19, Feb. 1996.
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2
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D. Epsufin, "Chromatic Raises the Multimedia Bar," Microprocessor Report, pp. 23-27, Oct. 23, 1995.
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3
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A. Chandrakasan, A. Burstein, and R. W. Broderson, "A Low Power Chipset for Portable Multimedia Applications," in ISSCC Dig. Tech. Papers, pp. 82-83, Feb. 1994.
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4
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D. B. Lidsky and J. M. Rab~y, "Low-Power Design of Memory Intensive Functions," in Symp. Low Power Electronics, Dig. Tech. Papers, pp. 16-17, Oct. 1994.
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5
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B. M. Gordon, T. H. Meng, and N. Chaddha, "A 1.2mW Video-Rate 2D Color Sued Decoder," in ISSCC Dig. Tech. Papers, pp. 290-291, Feb. 1995.
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6
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T. Baji, et al., "HX24 24-bit Fixed Point Digital Signal Processor," in Proc. ICSPAT, pp. 622-629, Oct. 1993.
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7
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A. Kiuchi, T. Nakagawa, T. Baji, and K. Kaneko, "Digital Signal Processor Supporting Two Types of Instruction Sets," Electronics and Communications in Japan, Part 3, Vol. 78, No. 6, pp. 20-29, 1995.
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8
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T. Burd and B. Peters, "A Power Analysis of a Microprocessor: A Study of an Implementation of the MIPS R3000 Architecture," Technical Report ERL, University of California, Berkeley, May 1994. http:/ fmfopad.eecs.berkeley.edu:80flmnffgl~/r3(~/total.html.
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9
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Y. Shimazald, et al., "An Autcmmfic-Power-Save Cache Memory for Low.Power RISC ~" in Syrup. Low Power Electronics Dig. Tech. Papers, pp. 58-59, Oct. 1995.
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10
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H. Kojima, D. J. Gorny, K. Nitta, and K. Sasaki, "Power Analysis of a Programmable DSP for Architectme /Program Optimization," in Syrup. Low Power Electronics Dig. Tech. Papers, pp. 26-27, Oct. 1995.
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CITED BY 5
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R. S. Bajwa , N. Schumann , H. Kojima, Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP, Proceedings of the 1997 international symposium on Low power electronics and design, p.137-142, August 18-20, 1997, Monterey, California, United States
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J. S. Hu , N. Vijaykrishnan , S. Kim , M. Kandemir , M. J. Irwin, Scheduling Reusable Instructions for Power Reduction, Proceedings of the conference on Design, automation and test in Europe, p.10148, February 16-20, 2004
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