A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications

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A graded-channel MOS (GCMOS) VLSI technology for low power DSP applications

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 129 - 132

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

J. Ma	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ
H. Liang	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ
M. Kaneshiro	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ
C. Kyono	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ
R. Pryor	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ
K. Papworth	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ
S. Cheng	Advanced Custom Technologies, Motorola, 2200 W.Broadway Rd., Mesa, AZ

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Y. Okumura, et al., IEDM Tech. Dig., p 391 (1990).
	2	H. Yoshimura, IEDM Tech. Dig., p.909 (1992).
	3	M. Aoki, et al., IEEE Electron Device Lett., vol. 13, p.50 (1992).
	4	A. Chatterjee, et al., IEDM Tech. Dig., p.87 (1994).
	5	T. Andoh, et al., 1EDM Tech. Dig., p.79 (1994).