Short circuit power consumption of glitches

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Short circuit power consumption of glitches

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 125 - 128

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

D. Rabe	FB3 - OFFIS, Escherweg 2, 26121 Oldenburg, Germanya and FB10 - Dep. of Computer Science, University of Oldenburg, 26111 Oldenburg, Germany
W. Nebel	FB3 - OFFIS, Escherweg 2, 26121 Oldenburg, Germanya and FB10 - Dep. of Computer Science, University of Oldenburg, 26111 Oldenburg, Germany

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. Rabe , W. Nebel, New approach in gate-level glitch modelling, Proceedings of the conference on European design automation, p.66-71, September 1996, Geneva, Switzerland
	2	Farid N. Najm, Power estimation techniques for integrated circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.492-499, November 05-09, 1995, San Jose, California, United States
	3	C.-S. Ding .... ;A comparative Study of Switching Activity Estimation Techniques; PATMOS'95, Oldenburg
	4	B. Davari .... ; CMOS Scaling for High Performance and Low Power:..; Proceedings of the IEEE, April 1995, pp. 595-606
	5	A.P. Chandrakasan .... ; Minimizing Power Consumption in Digital CMOS Circuits; Proceedings of the IEEE, April 1995, pp. 498-523
	6	H.J.M. Veendrick; Short-Circuit Dissipation of Static CMOS Circuin7 and its Impact on the Design of Buffer Circuits; IEEE J. of Solid State Circuits, 1984, pp. 468-473
	7	N. Hedenstierna .... ; CMOS Circuit Speed and Buffer Optimization; IEEE Trans. on CAD, 1987, pp. 270-281
	8	J. Leijten , J. van Meerbergen , J. Jess, Analysis and reduction of glitches in synchronous networks, Proceedings of the 1995 European conference on Design and Test, p.398, March 06-09, 1995
	9	M. Favalli , L. Benini, Analysis of glitch power dissipation in CMOS ICs, Proceedings of the 1995 international symposium on Low power design, p.123-128, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224103]
	10	C. Metra .... ; Glitch Power Dissipation Model; PATMOS'95, pp. 175-189
	11	M. Eisele .... ; Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Power at Logic Level; PATMOS'95, pp. 190-201
	12	D. Rabe .... ; Comparison of Different Gate Level Glitch Models; PATMOS'96
	13	M.A. Ortega .... ;Bounds on the Hazard Consumption in Modular Static CMOS Circuits; a talk on PATMOS'94, Barcelona, Spain, unpublished
	14	R. Burch .... ; A Monte Carlo Approach for Power Estimation; IEEE Tr. on VLSI Systems, Vol. 1, March 1993, pp. 63-71
	15	D. Rabe; ...: CMOS Library-Characterization for Power Consumption. PATMOS'94, 1994, pp. 94-105