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Effects of correlations on accuracy of power analysis—an experimental study
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 113 - 116  
Year of Publication: 1996
ISBN:0-7803-3571-6
Authors
P. Schneider  Siemens AG, ZFE T SE 5, D-81730 Munich and Inst. of EDA, TU-Munich, D-80290 Munich
S. Krishnamoorthy  Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA
Sponsors
IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 13,   Citation Count: 2
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. Deng, Y. Shiau, and K. Loh, "Time Domain Current Waveform Simulation of CMOS Circuits," in IEEE/ACMICCAD, pp. 208- 211, Nov. 1988.
 
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S. Chowdhury and J. S. Barkatullah, "Estimation of Maximum Current in MOS IC Logic Circuits," IEEE Transactions on CAD, vol. 1, pp. 63 - 71, Jan. 1993.
 
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C.M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation," in Sixteenth Eulvpean Solid-State Cilruits Conference (ESSCIRC' 90), pp. 61 - 64, Sept. 1990.
 
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R. Burch, F. Najm, R Yang, and T. Trick, "A Monte Carlo Approach for Power Estimation," IEEE Transactions on VLSI, pp. 63 - 71, 1993.
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C.-Y. Tsui, M. Pedram, and A. M. Despain, "Power Efficient Technology Decomposition and Mapping Under an Extended Power Consumption Model," IEEE Transactions on CAD, vol. 13, pp. 1110-1122, Sept. 1994.
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R H. Schneider and B. Wurth, "Transition probability estimation for combinational and sequential circuits," in International Workshop on Logic Synthesis (IWLS), pp. P4bl - P4bl0, May 1995.
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M. Eisele and J. Berthold, "Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Power at Logic Level," in International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Oct. 1995.
 
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A. Papoulis, P1vbability, Random Variables and Stochastic P1vcesses. McGraw- Hill, 1991.
 
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R H. Schneider, "PAPSAS: A Fast Switching Activity Simulator," in International Workshop on Power and Timing Modeling, Optimization and Simulation (PAT- MOS), pp. 350 - 360, Oct. 1995.
 
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Synopsys, Inc., VSS plvduct reference manual, 1995.


Collaborative Colleagues:
P. Schneider: colleagues
S. Krishnamoorthy: colleagues