Gate-level current waveform simulation of CMOS integrated circuits

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Gate-level current waveform simulation of CMOS integrated circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 109 - 112

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

Alessandro Bogliolo	CSL, Stanford University, Stanford, CA
Luca Benini	CSL, Stanford University, Stanford, CA
Giovanni De Micheli	CSL, Stanford University, Stanford, CA
Bruno Riccó	DEIS, University of Bologna, Bologna, I-40136

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 16, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	F. Najm et al., "CREST: a Current Estimator for CMOS Circuits," in Proc. of IEEE ICCAD, 1988.
	2	Richard Burch , Farid Najm , Ping Yang , Dale Hocevar, Pattern-independent current estimation for reliability analysis of CMOS circuits, Proceedings of the 25th ACM/IEEE conference on Design automation, p.294-299, June 12-15, 1988, Atlantic City, New Jersey, United States
	3	H. Kriplani et al., "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circults: Algorithms, Signal Correlations, and Their Resolution," IEEE Transaction on CAD, vol. 14, no. 8, 1995.
	4	S. Chowdhury et al., "Current Estimation in MOS IC Logic Circuits," in Proc. of IEEE ICCAD, 1988.
	5	S. Chowdury et al., "Estimation of Maximum Currents in MOS IC Logic Circuits," IEEE Transaction on CAD, vol. 9, no. 6, 1990.
	6	U. Jagau, "SIMCURRENT - An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits," in Proc. of IEEE ICCAD, 1990.
	7	F. Rouatbi , B. Haroun , A. J. Al-Khalili, Power estimation tool for sub-micron CMOS VLSI circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.204-209, November 1992, Santa Clara, California, United States
	8	A. Nabavi-Lishi , Nicholas Rumin, Delay and bus current evaluation in CMOS logic circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.198-203, November 1992, Santa Clara, California, United States
	9	A. Nabavi-Lishi et al., "Inverter Models of CMOS Gates for Supply Current and Delay Evaluation," IEEE Transaction on CAD, vol. 13, no. 10, 1994.
	10	A. Deng et al., "Time Domain Current Waveform Simulation of CMOS Circuits," in Proc. of IEEE ICCAD, 1988.
	11	A. Deng, "Power Analysis For CMOS/BiCMOS Circuits," in Proc. of IWLPD, 1994.
	12	A. Bogliolo et al., "Accurate Logic Level Power Estimation," in Proc. of IEEE SLPE, 1995.
	13	T. Burd, "Current Estimation in MOS IC Logic Circuits," in M. S. Report UC Berkeley, UCB/ERLM94/89.

CITED BY 4

	Arindam Mukherjee , Krishna Reddy Dusety , Rajsaktish Sankaranarayan, A practical CAD technique for reducing power/ground noise in DSM circuits, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Srinivas Bodapati , Farid N. Najm, High-level current macro-model for power-grid analysis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	P. Vuillod , L. Benini , A. Bogliolo , G. De Micheli, Clock skew optimization for peak current reduction, Proceedings of the 1996 international symposium on Low power electronics and design, p.265-270, August 12-14, 1996, Monterey, California, United States
	L. Benini , P. Vuillod , A. Bogliolo , G. De Micheli, Clock Skew Optimization for Peak Current Reduction, Journal of VLSI Signal Processing Systems, v.16 n.2-3, p.117-130, June/July 1997