Energy-recovery CMOS for highly pipelined DSP designs

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Energy-recovery CMOS for highly pipelined DSP designs

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 101 - 104

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

W. Athas	USC/Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, CA
W. Liu	USC/Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, CA
L. Svensson	USC/Information Sciences Institute, 4676 Admiralty Way, Marina del Rey, CA

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

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Downloads (6 Weeks): 4, Downloads (12 Months): 16, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	W. Athas, "Energy-Recovery CMOS," in J. Rabaey, M. Pedram (Eds)Low-Power Design Methodologies, Kluwer Academic Press, 1996.
	2	L. Svensson , W. Athas , R. Wen, A sub-CV2 pad driver with 10 ns transition time, Proceedings of the 1996 international symposium on Low power electronics and design, p.105-108, August 12-14, 1996, Monterey, California, United States
	3	W.C. Athas, J. Svensson, N. Tzartzanis, "A Resonant Signal Driver For Two-phase, Almost-non-overlapping Clocks," International Symposium on Circuits and Systems, May 1996.
	4	C. L. Seitz, A.H. Frey, S. Mattisson, S.D. Rabin, D.A. Speck, J.L.A. van de Snepscheut. Hot-clock NMOS. In Proc. of the 1985 Chapel Hill Conference on VLSI, pp. 1-17, 1985.
	5	Phillip J. Duncan , Shobana Swamy , Rajeev Jain, Low-power DSP circuit design using bit-level pipelined maximally-parallel architectures, Proceeding of the 1993 symposium on Research on integrated systems, p.266-275, February 1993, Seattle, Washington, United States
	6	C. Nagendra, R.M. Owens, M.J. Irwin, "Low power considerations in the design of pipelined FIR filters," 1995 IEEE Symposium on Low-Power Electronics, Oct. 1995.
	7	E Yang and R. Jain. An FIR filter generator. In Brodersen (Ed), Anatomy of a silicon compiler, Chapter 18. Kluwer, 1992.
	8	N. Tzartzanis , W. C. Athas, Design and analysis of a low-power energy-recovery adder, Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95), p.66, March 16-18, 1995