Transition reduction in carry-save adder trees

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Transition reduction in carry-save adder trees

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 85 - 88

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

P. Larsson	Bell Laboratories, 101 Crawfords Corner Rd., Holmdel, NJ
C. Nicol	Bell Laboratories, 101 Crawfords Corner Rd., Holmdel, NJ

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

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Downloads (6 Weeks): 11, Downloads (12 Months): 24, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. Sakuta, W. Lee, RT. Balsara, "Delay Balanced Multipliers for Low Power/Low Voltage DSP Core", IEEE Symposium on Low Power Electronics, Oct. 1995.
	2	Kaushik Roy , Sharat Prasad, SYCLOP: Synthesis of CMOS Logic for Low Power Applications, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.464-467, October 11-14, 1992
	3	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	4	G. Goto, T. Sato, M. Nakajima, T. Sukemura, "A 54x54-b Regularly Structured Tree Multiplier", IEEE J. of Solid-State Circuits, vol. 27, no. 9, pp. 1229-1236, Sept. 1992.
	5	N. Ohkubo, M. Suzuki, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, Y. Nakagome, "A 4.4ns CMOS 54 x 54-b Multiplier Using Pass-Transistor Multiplexer", IEEE J. of Solid-State Circuits, vol. 30, No. 3, March 1995.
	6	Z. Guan , P. Thomson , A. E. A. Almaini, A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.298-301, October 10-12, 1994
	7	B. Ackland, R. Clark, "Event-EMU: An Event Driven Timing Simulator for MOS VLSI Circuits", IEEE Int. Conf. on Computer- Aided Design (ICCAD), pp. 80-83, 1989.