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Switching activity analysis for sequential circuits using Boolean approximation method
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 79 - 84  
Year of Publication: 1996
ISBN:0-7803-3571-6
Authors
T. Uchino  Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
F. Minami  Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
M. Murakata  Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
T. Mitsuhashi  Semiconductor DA & Test Engineering Center, Toshiba Corp., 580-1, Horikawa-cho, Saiwai-ku, Kawasaki 210, Japan
Sponsors
IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 13,   Citation Count: 0
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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S.Ercolani, M.Favalli, M.Damiani, P.Olivo, B.Ricc5, "Estimate of Signal Probability in Combinational Logic Networks", European Test Conf., pp.132-138, 1989.
 
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Collaborative Colleagues:
T. Uchino: colleagues
F. Minami: colleagues
M. Murakata: colleagues
T. Mitsuhashi: colleagues