A novel methodology for transistor-level power estimation

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A novel methodology for transistor-level power estimation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 67 - 72

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

S. Huang	Dept. of Electrical & Computer Engrineering, Univ. of California, Santa Barbara, Santa Barbara, CA
K. Cheng	Dept. of Electrical & Computer Engrineering, Univ. of California, Santa Barbara, Santa Barbara, CA
K. Chen	Fujitsu Labs. of America, 3350 Scott Blvd. Bldg 34, Santa Clara, CA
T. Lee	Fujitsu Labs. of America, 3350 Scott Blvd. Bldg 34, Santa Clara, CA

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 19, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. M. Kang, "Accurate Simulation of Power Dissipation in VLSI Circuits," IEEE Journal of Solid State Circuits, vol. SC-21, no. 5, pp. 889-891, (Oct. 1986).
	2	M. A. Cirit, "Estimating Dynamic Power Consumption of CMOS Circuits," Proceedings of ICCAD, pp. 534- 537, (Nov. 1987).
	3	A. C. Deng, Y. C. Shiau and K. H. Loh, "Time Domain Current Waveform Simulation of CMOS Circuits," Pro-ceedings of ICCAD, pp. 208-211, (Nov. 1988).
	4	G. Y. Yacoub and W. H. Ku, "An Accurate Simulation Technique for Short-Circuit Power Dissipation Based on Current Component Isolation," IEEE International Sym-posium on Circuits and Systems, pp. 1157-1161, (1989).
	5	F. Najm, "Transition Density: A New Measure of Activ-ity in Digital Circuit," IEEE Trans. on Computer-Aided Design, vol. 12, no. 2, pp. 310-323, (1993).
	6	PowerMill Reference Manual, Version 2.7.1, EPIC Design Technology, (Aug. 1992).
	7	A. Ghosh , S. Devadas , K. Keutzer , J. White, Estimation of average switching activity in combinational and sequential circuits, Proceedings of the 29th ACM/IEEE conference on Design automation, p.253-259, June 08-12, 1992, Anaheim, California, United States
	8	Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
	9	Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
	10	R. Burch, F. Najm, P. Yang and T. Trick, "A Monte Carlo Approach for Power Estimation," IEEE Trans. on VLSI System, vol. 1, no. 1, pp. 63-71, (March 1993).
	11	Anthony M. Hill , Sung-Mo Steve Kang, Determining accuracy bounds for simulation-based switching activity estimation, Proceedings of the 1995 international symposium on Low power design, p.215-220, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224119]
	12	José Monteiro , Srinivas Devadas, Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs, Proceedings of the 1995 international symposium on Low power design, p.33-38, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224088]
	13	Premal Buch , Shen Lin , Vijay Nagasamy , Ernest S. Kuh, Techniques for fast circuit simulation applied to power estimation of CMOS circuits, Proceedings of the 1995 international symposium on Low power design, p.135-138, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224105]
	14	D. I. Cheng, M. Marek-Sadowska and K.-T. Cheng, "Speeding Up Power Estimation by Topological Analy-sis, "Proceedings of IEEE Custom Integrated Circuit Conference, pp. 623-626, (May 1995).
	15	Shi-Yu Huang , Kuang-Chien Chen , Kwang-Ting Cheng , Tien-Chien Lee, Compact vector generation for accurate power simulation, Proceedings of the 33rd annual conference on Design automation, p.161-164, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240548]

CITED BY 4

	Luca Benini , Giovanni De Micheli , Enrico Macii , Massimo Poncino , Riccardo Scarsi, Fast power estimation for deterministic input streams, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.494-501, November 09-13, 1997, San Jose, California, United States
	Alberto Macii , Enrico Macii , Massimo Poncino , Riccardo Scarsi, Stream synthesis for efficient power simulation based on spectral transforms, Proceedings of the 1998 international symposium on Low power electronics and design, p.30-35, August 10-12, 1998, Monterey, California, United States
	Byunggyu Kwak , Eun Sei Park, An optimization-based error calculation for statistical power estimation of CMOS logic circuits, Proceedings of the 35th annual conference on Design automation, p.690-693, June 15-19, 1998, San Francisco, California, United States
	Yen-Fong Lee , Shi-Yu Huang , Sheng-Yu Hsu , I-Ling Chen , Cheng-Tao Shieh , Jian-Cheng Lin , Shih-Chieh Chang, Power estimation starategies for a low-power security processor, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China