A 1-V 1-Mb SRAM for portable equipment

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A 1-V 1-Mb SRAM for portable equipment

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 61 - 66

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

H. Morimura	NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa-ken 243-01, Japan
N. Shibata	NTT LSI Laboratories, 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa-ken 243-01, Japan

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mutoh, el al., "A 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application," ISSCC Dig. Tech. Papers, pp. 168-169, Feb. 1996.
	2	Izumikawa, el al., "A 0.9-V 100-MI-Iz 4-roW 2-ram2 16-b DSP Core," ISSCC Dig. Tech. Papers, pp. 84-85, Feb. 1995.
	3	Date, el al., "I-V 30-MI-Iz Memory-Macrocell-Circuit Technology with a 0.5-#m Multi-threshold CMOS," IEEE Symp. on Low Power Electronics Dig. Tech. Papers, pp. 90-91, Sept. 1994.
	4	Mizuno, el al., "A 1-V 100-MI-Iz 10-roW Cache using Separated Bit-Line Memory Hierarchy and Domino Tag Comparators," ISSCC Dig. Tech. Papers, pp. 152-153, " Feb. 1996.
	5	Takashima, el al., "Standby/active Mode Logic for Sub-lV Operating ULSI Memory" IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 441-447, Apr. 1994.

CITED BY 5

	You-Sung Chang , Chong-Min Kyung, Conforming block inversion for low power memory, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.1, p.15-19, 2/1/2002
	F. Catthoor, Energy-delay efficient data storage and transfer architectures: circuit technology versus design methodology solutions, Proceedings of the conference on Design, automation and test in Europe, p.709-715, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Francky Catthoor, Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems, Journal of VLSI Signal Processing Systems, v.21 n.3, p.219-231, July 1999
	Y. Nakagome , M. Horiguchi , T. Kawahara , K. Itoh, Review and future prospects of low-voltage RAM circuits, IBM Journal of Research and Development, v.47 n.5-6, p.525-552, September 2003
	Kiyoo Itoh, Ultralow-voltage memory circuits, Design of system on a chip: devices & components, Kluwer Academic Publishers, Norwell, MA, 2004