A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

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A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1996 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 49 - 54

Year of Publication: 1996

ISBN:0-7803-3571-6

Authors

H. Yamauchi	Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., 3-1-1, Yagumo-nakamachi, Moriguchi, Osaka 570 Japan
T. Iwata	Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., 3-1-1, Yagumo-nakamachi, Moriguchi, Osaka 570 Japan
H. Akamatsu	Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., 3-1-1, Yagumo-nakamachi, Moriguchi, Osaka 570 Japan
A. Matsuzawa	Semiconductor Research Center, Matsushita Electric Industrial Co., Ltd., 3-1-1, Yagumo-nakamachi, Moriguchi, Osaka 570 Japan

Sponsors

IEEE-CAS : Circuits & Systems
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Press Piscataway, NJ, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Mizuno, et. al, " Driving Source-Line(DSL) Cell Architecture for Sub-l-V High-Speed Low-Power Applications." in Symp. on VLSI circuits, pp. 25-26, Jun.1995.
	2	K. Itoh, et. al, " A Deep Sub-V, Single Power-Supply .SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load" in Symp. on VLSI circuits, Jun.1996, session 12.4.
	3	J. Dickson et al, "On-Chip high voltage generation in NMOS integrated circuits using an improved voltage multiplier technique." IEEE J.SSC,vol.SC-11,pp.374- 378,1976
	4	H. Yamauchi, et al, "A 0.8V/100MHz/sub-5mW- Operated Mega-bit SRAM Cell Architecture with Charge- Recycle Offset-Source Driving (OSD) Scheme" in Symp. on VLSI circuits, Jun. 1996, session 12.1.