Recent developments in high-level synthesis

ABSTRACT

We survey recent developments in high level synthesis technology for VLSI design. The need for higher-level design automation tools are discussed first. We then describe some basic techniques for various subtasks of high-level synthesis. Techniques that have been proposed in the past few years (since 1994) for various subtasks of high-level synthesis are surveyed. We also survey some new synthesis objectives including testability, power efficiency, and reliability.

REFERENCES

• 1: ACHATZ, H. 1993. Extended 0/1 LP formulation for the scheduling problem in high level synthesis. In Proceedings, EURO-DAC'93 with EURO-VHDL'93, 226-231.
• 2: Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
• 3: Mohammed Aloqeely , C. Y. Roger Chen, Sequencer-based data path synthesis of regular iterative algorithms, Proceedings of the 31st annual conference on Design automation, p.155-160, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196317]
• 4: J. Bhasker , Huan-Chih Lee, An Optimizer for Hardware Synthesis, IEEE Design & Test, v.7 n.5, p.20-36, September 1990 [doi>10.1109/54.60604]
• 5: CAMPOSANO, R. 1991. Path-based scheduling for synthesis. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 10, 1 (Jan.), 85-93.
• 6: Raul Camposano , Wayne H. Wolf, High-Level VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1991
• 7: CAMPOSANO, R., BERGAMASCHI, R. A., HAYNES, C., PAYER, M., AND WU, S.M. 1991. The IBM high level synthesis system. In High Level VLSI Synthesis, R. Camposano and W. Wolf, Eds. Kluwer Academic, Norwell, MA.
• 8: Viraphol Chaiyakul , Daniel D. Gajski , Loganath Ramachandran, High-level transformations for minimizing syntactic variances, Proceedings of the 30th international conference on Design automation, p.413-418, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164956]
• 9: Samit Chaudhuri , Robert A. Walker, Computing lower bounds on functional units before scheduling, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.2, p.273-279, June 1996 [doi>10.1109/92.502199]
• 10: Samit Chaudhuri , Robert A. Walker , John E. Mitchell, Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.456-471, Dec. 1994 [doi>10.1109/92.335014]
• 11: CHU, C. M., POTKONJAK, M., THALER, M., AND RABAEY, J. 1989. HYPER: An interactive synthesis environment for high performance real time applications. In Proceedings of the International Conference on Computer Design (ICCD) (Oct.), 432-435.
• 12: John A. Darringer , William H. Joyner, Jr., A new look at logic synthesis, Proceedings of the 17th conference on Design automation, p.543-549, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804583]
• 13: DHODHI, M. K., AHMAD, I., AND ISMAEEL, A.A. 1995. High level synthesis of data paths for easy testability. IEE Proc. Circuits, Devices Syst. 142, 4 (Aug.), 209-216.
• 14: DHODHI, M. K., HIELSCHER, F. H., STORER, R. H., AND BHASKER, g. 1995. Datapath synthesis using a problem-space genetic algorithm. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 14, 8 (Aug.), 934-944.
• 15: ERNST, R. AND HENKEL, J. 1992. Hardware-software codesign of embedded controllers based on hardware extraction. In handout from The First International Workshop on Hardware- Software Codesign.
• 16: EWERING, C. 1990. Automatic high level synthesis of partitioned busses. In Digest of Technical Papers, International Conference on Computer-Aided Design (ICCAD) (Santa Clara, CA, Nov.), 304-307.
• 17: Yung-Ming Fang , D. F. Wong, Simultaneous functional-unit binding and floorplanning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.317-321, November 06-10, 1994, San Jose, California, United States
• 18: M. L. Flottes , D. Hammad , B. Rouzeyre, High-level synthesis for easy testability, Proceedings of the 1995 European conference on Design and Test, p.198, March 06-09, 1995
• 19: Thomas E. Fuhrman, Industrial extensions to university high level synthesis tools: Making it work in the real world, Proceedings of the 28th conference on ACM/IEEE design automation, p.520-525, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127725]
• 20: Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
• 21: GEBOTYS, C.H. 1994. An optimization approach to the synthesis of multichip architectures. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 2, 1, 11-20.
• 22: GIRCZYC, E. F. 1987. Loop winding--a data flow approach to functional pipelining. In Proceedings of the International Symposium on Circuits and Systems, 382-385.
• 23: GIRCZYC, E. F., BUHR, R. J. A., AND KNIGHT, J.P. 1985. Applicability of a subset of Ada as an algorithmic hardware description language for graph-based hardware compilation. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 4, 2 (April).
• 24: Laurence Goodby , Alex Orailoglu , Paul M. Chau, Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.323-326, October 10-12, 1994
• 25: GOOSSENS, G., RABAEY, J., VANDEWALLE, J., AND DE MAN, H. 1990. An efficient microcode compiler for application specific DSP processors. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 9, 9 (Sept.), 925-937.
• 26: Douglas M. Grant , Peter B. Denyer, Address Generation for array access based on modulus m counters, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
• 27: Rajesh Gupta , Melvin A. Breuer, Partial scan design of register-transfer level circuits, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.25-46, Aug./Oct. 1995 [doi>10.1007/BF00993312]
• 28: GUPTA, R. AND DE MICHELI, G. 1990. Partitioning of functional models of synchronous digital systems. In Digest of Technical Papers, International Conference on Computer-Aided Design (ICCAD) (Santa Clara, CA, Nov.), 216-219.
• 29: GUPTA, R. K. AND DE MICHELI, G. 1992. System level synthesis using re-programmable components. In Proceedings of the European Conference on Design Automatio (EDAC) (Amsterdam, the Netherlands), 2-7.
• 30: HARTLEY, R. AND CASAVANT, A. 1989. Tree-height minimization in pipelined architectures. In Digest of Technical Papers, International Conference on Computer-Aided Design (ICCAD) (Santa Clara, CA, Nov.), 112-115.
• 31: M. J. M. Heijligers , L. J. M. Cluitmans , J. A. G. Jess, High-level synthesis scheduling and allocation using genetic algorithms, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.11-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224842]
• 32: Charles Y. Hitchcock, III , Donald E. Thomas, A method of automatic data path synthesis, Proceedings of the 20th conference on Design automation, p.484-489, June 27-29, 1983, Miami Beach, Florida, United States
• 33: Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel, Enhancing high-level control-flow for improved testability, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.322-328, November 10-14, 1996, San Jose, California, United States
• 34: Chu-Yi Huang , Yen-Shen Chen , Youn-Long Lin , Yu-Chin Hsu, Data path allocation based on bipartite weighted matching, Proceedings of the 27th ACM/IEEE conference on Design automation, p.499-504, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123350]
• 35: Steve C.-Y. Huang , Wayne H. Wolf, How datapath allocation affects controller delay, Proceedings of the 7th international symposium on High-level synthesis, p.158-163, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
• 36: HWANG, C.-T., LEE, J.-H., AND HSU, Y.-C. 1991. A formal approach to the scheduling problem in high level synthesis. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 10, 4 (April), 464-475.
• 37: IEEE 1988. Sehwa: A software package for synthesis of pipelined from behavioral specifications. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 7, 3 (March), 356-370.
• 38: KARNIK, T., TENG, C.-C., AND KANG, S.-M. 1995. High-level hot carrier reliability-driven synthesis using macro-models. In Proceedings, the IEEE 1995 Custom Integrated Circuits Conference (Santa Clara, CA) 65-68.
• 39: KAWAGUCHI, T. AND TODAKA, T. 1995. Operation scheduling by annealed neural networks. IEICE Trans. Fund. Electr. Commun. Comput. Sci. E78-A, 6 (June), 656-663.
• 40: KERNIGHAN, K. H. AND LIN, S. 1970. An efficient heuristic procedure for partitioning graph. Bell Syst. Tech. J. 49, 2 (Feb.), 291-307.
• 41: Nand Kumar , Srinivas Katkoori , Leo Rader , Ranga Vemuri, Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems, IEEE Design & Test, v.12 n.3, p.70-84, September 1995 [doi>10.1109/MDT.1995.466383]
• 42: Taewhan Kim , C. L. Liu, A new approach to the multiport memory allocation problem in data path synthesis, Integration, the VLSI Journal, v.19 n.3, p.133-160, Nov. 1995 [doi>10.1016/0167-9260(95)00009-5]
• 43: KIM, T., YONEZAWA, N., LIU, J. W. S., AND LIU, C. L. 1994. A scheduling algorithm for conditional resource sharing--a hierarchical reduction approach. IEEE Trans. Comput.- Aided Des. Integ. Circuits Syst. 13, 4 (April), 425-437.
• 44: David J. Kolson , Alexandru Nicolau , Nikil Dutt, Integrating program transformations in the memory-based synthesis of image and video algorithms, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.27-30, November 06-10, 1994, San Jose, California, United States
• 45: Kayhan Küçükçakar , Alice C. Parker, Data path tradeoffs using MABAL, Proceedings of the 27th ACM/IEEE conference on Design automation, p.511-516, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123388]
• 46: Kayhan Kükçakar , Alice C. Parker, CHOP: A constraint-driven system-level partitioner, Proceedings of the 28th conference on ACM/IEEE design automation, p.514-519, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127724]
• 47: F. J. Kurdahi , A. C. Parker, REAL: a program for REgister ALlocation, Proceedings of the 24th ACM/IEEE conference on Design automation, p.210-215, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37920]
• 48: LAGNESE, E. AND THOMAS, D. 1991. Architectural partitioning for system level partitioner. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 10, 7 (July), 847-860.
• 49: Dirk Lanneer , Marco Cornero , Gert Goossens , Hugo De Man, Data routing: a paradigm for efficient data-path synthesis and code generation, Proceedings of the 7th international symposium on High-level synthesis, p.17-22, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
• 50: LANNEER, D., NOTE, S., DEPUYDT, F., PAUWELS, M., CATTHOOR, F., GOOSSENS, G., AND DE MAN, H. 1990. Architectural synthesis for medium and high throughput signal processing with the new CATHEDRAL environment. In High Level VLSI Synthesis, R. Camposano and W. Wolf, Eds., Kluwer Academic, Norwell, MA.
• 51: Birger Landwehr , Peter Marwedel , Rainer Dömer, OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming, Proceedings of the conference on European design automation, p.90-95, September 19-23, 1994, Grenoble, France
• 52: LEDEUX, S., ET AL. 1993. The Siemens high level synthesis system CALLAS. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 1, 3 (Sept.), 144-153.
• 53: Hae-Dong Lee , Sun-Young Hwang, A scheduling algorithm for multiport memory minimization in datapath synthesis, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.16-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224847]
• 54: LEE, T.-F., WU, A. C.-H., LIN, Y.-L., AND GAJSKI, D. 1994. A transformation-based method for loop folding. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 13, 4 (April), 439-450.
• 55: P. E. R. Lippens , J. L. van Meerbergen , A. van der Werf , W. F. J. Verhaegh , B. T. McSweeney , J. O. Huisken , O. P. McArdle, PHIDEO: a silicon compiler for high speed algorithms, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
• 56: Tai Ly , David Knapp , Ron Miller , Don MacMillen, Scheduling using behavioral templates, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.101-106, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217514]
• 57: LY, T. A. AND MOWCHENKO, g.T. 1993. Applying simulated evolution to high level synthesis. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 12, 3 (March), 389-409.
• 58: Raul San Martin , John P. Knight, Power-profiler: optimizing ASICs power consumption at the behavioral level, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.42-47, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217504]
• 59: Michael C. McFarland, Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.474-480, July 1986, Las Vegas, Nevada, United States
• 60: MCFARLAND, M. C. AND KOWALSKI, T.J. 1990. Incorporating bottom-up design into hardware synthesis. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 9, 9 (Sept.), 938-950.
• 61: MECHA, H., FERNANDEZ, M., TIRADE, F., SEPTIEN, J., MOTES, D., AND OLCOZ, K. 1996. A method for area estimation of data path in high level synthesis. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 15, 2 (Feb.), 258-265.
• 62: Renu Mehra , Jan Rabaey, Exploiting regularity for low-power design, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.166-172, November 10-14, 1996, San Jose, California, United States
• 63: U. Lauther , Peter Duzy , Petra Michel, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, Norwell, MA, 1992
• 64: Giovanni De Micheli , David Ku , Frederic Mailhot , Thomas Truong, The Olympus Synthesis System, IEEE Design & Test, v.7 n.5, p.37-53, September 1990 [doi>10.1109/54.60605]
• 65: Ashutosh Mujumdar , Rajiv Jain , Kewal Saluja, Incorporating testability considerations in high-level synthesis, Journal of Electronic Testing: Theory and Applications, v.5 n.1, p.43-55, Feb. 1994 [doi>10.1007/BF00971962]
• 66: MUNCH, M., WEHN, N., AND GLESNER, M. 1995. Optimum simultaneous placement and binding for bit-slice architectures. In Proceedings of the Asia and South-Pacific Design Automation Conference (ASP-DAC) (Chiba, Japan), 735-740.
• 67: E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224523]
• 68: Alexandru Nicolau , Roni Potasmann, Incremental tree height reduction for high level synthesis, Proceedings of the 28th conference on ACM/IEEE design automation, p.770-774, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127767]
• 69: Alex Orailoglu , Daniel D. Gajski, Flow graph representation, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.503-509, July 1986, Las Vegas, Nevada, United States
• 70: ORAILOGLU, A. AND KARRI, R. 1994. Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures. IEEE Trans. Very Large Scale Integ. (VLSI) Syst. 2, 3 (Sept.), 304-311.
• 71: PANGRLE, B. M. AND GAJSKI, D. D. 1987. Design tools for intelligent silicon compilation. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 6, 6 (Nov.), 1098-1112.
• 72: In-Cheol Park , Chong-Min Kyung, Fast and near optimal scheduling in automatic data path synthesis, Proceedings of the 28th conference on ACM/IEEE design automation, p.680-685, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127750]
• 73: PARK, N. AND PARKER, A. 1988. Sehwa: A software package for synthesis of pipelined data path from behavioral specification. IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 7, 3 (March), 356-370.
• 74: PAULIN, P. G. AND KNIGHT, J.P. 1989. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 8, 6 (June), 661-679.
• 75: Massoud Pedram, Power minimization in IC design: principles and applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.1, p.3-56, Jan. 1996 [doi>10.1145/225871.225877]
• 76: POTKONJAK, M. AND RABAEY, g. 1994. Optimizing resource utilization using transformation. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 13, 3 (March), 277-292.
• 77: Miodrag Potkonjak , Mani Srivastava, Rephasing: a transformation technique for the manipulation of timing constraints, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.107-112, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217515]
• 78: Miodrag Potkonjak , Sujit Dey , Rabindra K. Roy, Synthesis-for-testability using transformations, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.78-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224961]
• 79: POWELL, S. R. AND CHAU, P.M. 1990. Estimating power dissipation of VLSI signal processing chip: The PFA technique. In Proceedings of VLSI Signal Processing IV, 250-259.
• 80: RABAEY, J., GUERRA, L., AND MEHRA, R. 1995. Design guidance in the power dimension. 1995 International Conference on Acoustics, Speech, and Signal Processing, 2837-2840.
• 81: Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
• 82: Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
• 83: D. Sreenivasa Rao , F. J. Kurdahi, Controller and datapath trade-offs in hierarchical RT-level synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.152-157, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
• 84: REESE, B. 1994. Using HYPER to teach datapath design techniques in an ASIC design course. In Proceedings, IEEE International ASIC Conference and Exhibit, 200-203.
• 85: RIM, M. AND JAIN, R. 1994. Lower-bound performance estimation for the high level synthesis scheduling problem. IEEE Trans. Comput.-Aided Des. Integ. Circuits Syst. 13, 4 (April), 451-458.
• 86: W Rosenstiel, Optimizations in high level synthesis, Microprocessing and Microprogramming, v.18 n.1-5, p.347-352, Dec. 1986 [doi>10.1016/0165-6074(86)90063-3]
• 87: SHARMA, A. AND JAIN, R. 1995. InSyn: Integrated scheduling for DSP applications. IEEE Trans. Signal Process. 43, 8 (Aug.), 1966-1977.
• 88: Ravibala Singh , John Knight, Concurrent testing in high-level synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.96-103, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
• 89: STANDARD VHDL LANGUAGE REFERENCE MANUAL. 1988. The Institute of Electrical and Electronics Engineers, Inc., New York.
• 90: Donald E. Thomas , Philip R. Moorby, The Verilog hardware description language (4th ed.), Kluwer Academic Publishers, Norwell, MA, 1998
• 91: Donald E. Thomas , Elizabeth D. Lagnese , John A. Nestor , Jayanth V. Rajan , Robert L. Blackburn , Robert A. Walker, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell, MA, 1989
• 92: TSAY, F.-S. AND HSU, Y.-C. 1990. Data path construction and refinement. In Digest of Technical Papers, International Conference on Computer-Aided Design (ICCAD) (Santa Clara, CA, Nov.), 308-311.
• 93: TSENG, C. g. AND SIEWIOREK, D. P. 1986. Automatic synthesis of data path on digital systems. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 5, 3 (July), 379-395.
• 94: UNALTUNA, M. K. AND PITCHUMANI, V. 1995. ANSA: A new neural net based scheduling algorithm for high level synthesis. In IEEE Symposium on Circuits and Systems, Vol 1 (Seattle, WA), 385-388.
• 95: F. Vahid , D. D. Gajski, Specification partitioning for system design, Proceedings of the 29th ACM/IEEE conference on Design automation, p.219-224, June 08-12, 1992, Anaheim, California, United States
• 96: WAKABAYASHI, Z. AND YOSHIMURA, T. 1989. A resource sharing control synthesis method for conditional branches. In Digest of Technical Papers, International Conference on Computer- Aided Design (ICCAD) (Santa Clara, CA, Nov.), 62-65.
• 97: WALKER, R. A. AND CAMPOSANO, R., EDS. 1991. A Survey of High Level Synthesis. Kluwer Academic, Norwell, MA.
• 98: WALKER, R. A. AND THOMAS, D.E. 1989. Behavioral transformations for algorithmic level IC design. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 8, 10 (Oct.), 1115-1128.
• 99: WANG, X. J. AND GRAINGER, S.R. 1994. The reduction of the number of equations in the ILP formulation for the scheduling problem in high level synthesis. In Proceedings, the Second International Conference on Concurrent Engineering and Electronic Design Automation (Bournemouth, UK), 483-487.
• 100: N. Wehn , H.-J. Herpel , T. Hollstein , P. Poechmueller , M. Glesner, High-level synthesis in a rapid-prototype environment for mechatronic systems, Proceedings of the conference on European design automation, p.188-193, November 1992, Congress Centrum Hamburg, Hamburg, Germany
• 101: WILSON, T. C., MUKHERJEE, N., GARG, M. K., AND BANERJI, D.K. 1995. An ILP solution for optimum scheduling, module and register allocation, and operation binding in datapath synthesis. VLSI Design 3, 1, 21-36.
• 102: ZIMMERMANN, G. 1980. MDS: The Mimola design method. J. Digital Syst. 4, 3, 337-369.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Data-path design

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Hardware description languages; Optimization; Automatic synthesis

General Terms:
Design, Experimentation, Languages, Reliability

Keywords:
VLSI design, design automation, design methodology, high level synthesis