Reduced instruction set computers

ABSTRACT

Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.

REFERENCES

• 1: Bernhard. R. More hardware means less software. 1EEE Specfrum 18. 12 (Dec. 1981). 30-37.
• 2: G. J. Chaitin, Register allocation & spilling via graph coloring, Proceedings of the 1982 SIGPLAN symposium on Compiler construction, p.98-105, June 23-25, 1982, Boston, Massachusetts, United States
• 3: Joseph A. Fisher, Very Long Instruction Word architectures and the ELI-512, Proceedings of the 10th annual international symposium on Computer architecture, p.140-150, June 13-17, 1983, Stockholm, Sweden
• 4: Hennessy. I.L. VLSI processor architecture. IEEE Trans. Comput. To be published.
• 5: Hopkins, M. A perspective on microcode. In Proceedings of the 21st Annual IEEE Computer Conference (Spring COMPCON 83) (San Francisco, Calif., Feb.). IEEE. New York, 1983, pp. 108-110.
• 6: Hopkins. M. Definition of RISC. In Proceedings of the Conference on High Level Language Computer Architecture (Los Angeles, Calif.. May). 1984.
• 7: Emmanuel-Manolis George Katevenis, Reduced instruction set computer architectures for vlsi (microprocessor, risc, multiple-windows - of - registers), 1983
• 8: Åmund Lunde, Empirical evaluation of some features of instruction set processor architectures, Communications of the ACM, v.20 n.3, p.143-153, March 1977 [doi>10.1145/359436.359442]
• 9: Patterson. D.A. Microprogramming. Sci. Am. 248, 3 (Mar. 1983). 36-43.
• 10: David A. Patterson, RISC watch, ACM SIGARCH Computer Architecture News, v.12 n.1, p.11-19, March 1984 [doi>10.1145/641602.641604]
• 11: Patterson. D.A., and S6quin. C. A VLSI RISC. Computer 15. 9 (Sept. 1982). 8-21.
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• 13: David Ungar , Ricki Blau , Peter Foley , Dain Samples , David Patterson, Architecture of SOAR: Smalltalk on a RISC, Proceedings of the 11th annual international symposium on Computer architecture, p.188-197, January 1984

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design, Performance