Directional bias and non-uniformity in FPGA global routing architectures

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Directional bias and non-uniformity in FPGA global routing architectures

Full text

Publisher Site , Pdf

Pdf (78 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 652 - 659

Year of Publication: 1997

ISBN:0-8186-7597-7

Authors

Vaughn Betz	Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 3G4
Jonathan Rose	Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 3G4

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 13, Citation Count: 11

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

ABSTRACT

This paper investigates the effect of the prefabricated routing track distribution on the area-efficiency of FPGAs. The first question we address is whether horizontal and vertical channels should contain the same number of tracks (capacity), or if there is a density advantage with a directional bias. Secondly, should the channels have a uniform capacity, or is there an advantage when capacities vary from channel to channel? The key result is that the most area-efficient global routing architecture is one with uniform (or very nearly uniform) channel capacities across the entire chip in both the horizontal and vertical directions. Several non-uniform and directionally-biased architectures, however, are fairly area-efficient provided that appropriate choices are made for the pin positions on the logic blocks and the logic array aspect ratio.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	2	Xilinx Inc., The Programmable Logic Data Book, 1994.
	3	AT & T Inc., ORCA Datasheet, 1994.
	4	Actel Inc., FPGA Data Book and Design Guide, 1994.
	5	Altera Inc., Data Book, 1993.
	6	B.K. Britton, et al., "Second Generation ORCA Architecture Utilizing 0.5~t Process Enhances the Speed and Usable Gate Capacity of FPGAs," IEEE Int. ASIC Conf., Sept. 1994, pp. 474-478.
	7	D. Tavana, W. Yee, S. Young, and B. Fawcett, "Logic Block and Routing Considerations for a New SRAM-Based FPGA Architecture," CICC, 1995, pp. 24.6.1 - 24.6.4.
	8	S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0, Tech. Report, Microelectronics Centre of North Carolina, 1991.
	9	E.M. Sentovich et al, "SIS: A System for Sequential Circuit Analysis," Tech. Report No. UCB/ERL M92/41, University of California, Berkeley, 1992.
	10	J. Cong and Y. Ding, "FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup- Table Based FPGA Designs," IEEE Trans. Computer- Aided Design, Jan. 1994, pp. 1-12.
	11	S. Kirkpatrick, C. D. Gelatt, Jr., and M. E Vecchi, "Optimization by Simulated Annealing," Science, May 13, 1983, pp. 671 - 680.
	12	Chih-Liang Eric Cheng, RISA: accurate and efficient placement routability modeling, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.690-695, November 06-10, 1994, San Jose, California, United States
	13	Carl Ebeling , Larry McMurchie , Scott A. Hauck , Steven Burns, Placement and routing tools for the Triptych FPGA, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.4, p.473-482, Dec. 1995 [doi>10.1109/92.475966]
	14	C. Y. Lee, "An Algorithm for Path Connections and its Applications," IRE Trans. Electron. Comput., Vol. EC-10, 1961, pp. 346 - 365.
	15	V. Betz and J. Rose, "On Biased and Non-uniform Global Routing Architectures and CAD Tools for FPGAs," Technical Report, University of Toronto, 1996.

CITED BY 13

	Guy G. F. Lemieux , Stephen D. Brown , Daniel Vranesic, On two-step routing for FPGAS, Proceedings of the 1997 international symposium on Physical design, p.60-66, April 14-16, 1997, Napa Valley, California, United States
	Peter Hallschmid , Steven J. E. Wilton, Detailed routing architectures for embedded programmable logic IP cores, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.69-74, February 2001, Monterey, California, United States
	Jason Helge Anderson , Stephen Dean Brown, An LPGA with foldable PLA-style logic blocks, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.244-252, February 22-25, 1998, Monterey, California, United States
	Michael Hutton , Jonathan Rose , Derek Corneil, Generation of synthetic sequential benchmark circuits, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.149-155, February 09-11, 1997, Monterey, California, United States
	Atsushi Takahara , Toshiaki Miyazaki , Takahiro Murooka , Masaru Katayama , Kazuhiro Hayashi , Akihiro Tsutsui , Takaki Ichimori , Ken-nosuke Fukami, More wires and fewer LUTs: a design methodology for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.12-19, February 22-25, 1998, Monterey, California, United States
	Om Agrawal , Herman Chang , Brad Sharpe-Geisler , Nick Schmitz , Bai Nguyen , Jack Wong , Giap Tran , Fabiano Fontana , Bill Harding, An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.17-26, February 21-23, 1999, Monterey, California, United States
	David Lewis , Vaughn Betz , David Jefferson , Andy Lee , Chris Lane , Paul Leventis , Sandy Marquardt , Cameron McClintock , Bruce Pedersen , Giles Powell , Srinivas Reddy , Chris Wysocki , Richard Cliff , Jonathan Rose, The stratixπ routing and logic architecture, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Peter Hallschmid , Steve J. E. Wilton, Routing architecture optimizations for high-density embedded programmable IP cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1320-1324, November 2005
	Mingjie Lin , Abbas El Gamal, A routing fabric for monolithically stacked 3D-FPGA, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
	Yajun Ran , M. Marek-Sadowska, An integrated design flow for a via-configurable gate array, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.582-589, November 07-11, 2004
	Hongbing Fan , Yu-Liang Wu , Ray Chak-Chung Cheung , Jiping Liu, Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes, IEEE Transactions on Computers, v.55 n.4, p.373-384, April 2006
	Muhammet Mustafa Ozdal , Martin D. F. Wong, Length-Matching Routing for High-Speed Printed Circuit Boards, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.394, November 09-13, 2003
	Luca Sterpone , Massimo Violante, A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs, IEEE Transactions on Computers, v.55 n.6, p.732-744, June 2006