The case for retiming with explicit reset circuitry

ABSTRACT

Retiming is often used to optimize synchronous sequential circuits for area or delay or both. If the latches that are retimed have a hardware reset value, the initial state of the circuit must also be retimed, i.e. an initial state must be derived for the retimed circuit. Previously, it has been suggested that this can be avoided if the hardware reset signals are represented explicitly. However, it was thought that this adds unnecessary area and restricts the space of possible retimings. In this paper we demonstrate that this is not the case. In addition, we show that this methodology does not require the restriction that all reset signals be asserted at the beginning of circuit operation--- a restriction that was imposed by existing algorithms for determining the retimed initial state. Finally we show how our explicit reset (ER) framework enables us to retime when some latches may be driven by different hardware resets, and some others may not have any hardware resets. We also consider the case where the resets are asynchronous. We expect these solutions to the "retimed initial state" problem to help increase the practical applicability of retiming.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Sequential circuits
      B.6.3 Design Aids
          Subjects: Optimization

General Terms:
Algorithms, Design, Performance, Theory, Verification

Keywords:
Retiming, initial state, reset state, synchronous reset, asynchronous reset