Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs

ABSTRACT

A sound IC design methodology must be supported by adequate manufacturability assessment tools. These tools should assist a designer in predicting IC manufacturing cost in as early a design stage as possible. In this paper a yield model is proposed that takes as input a standard cell netlist and produces as output a yield estimate without performing placement and routing. This yield model has been successfully used to predict the interconnect yield of standard cell designs that were implemented with two place and route tools. The proposed yield model can be used as a crucial component in the objective function of a circuit synthesis tool as well as in technology mapping optimization.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Measurement, Performance

Keywords:
Yield, Manufacturability, Interconnects, Synthesis, Standard Cell Designs.