Exploiting regularity for low-power design

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Exploiting regularity for low-power design

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International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 166 - 172

Year of Publication: 1997

ISBN:0-8186-7597-7

Authors

Renu Mehra	Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Jan Rabaey	Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 11

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 11

	Inki Hong , Miodrag Potkonjak , Ramesh Karri, Power optimization using divide-and-conquer techniques for minimization of the number of operations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.4 n.4, p.405-429, Oct. 1999
	Youn-Long Lin, Recent developments in high-level synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.1, p.2-21, Jan. 1997
	Lijun Gao , Keshab K. Parhi, Models for power consumption and power grid noise due to datapath transition activity, Proceedings of the 11th Great Lakes symposium on VLSI, p.121-126, March 2001, West Lafayette, Indiana, United States
	Philip Brisk , Adam Kaplan , Ryan Kastner , Majid Sarrafzadeh, Instruction generation and regularity extraction for reconfigurable processors, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Gareth Keane , Jonathan Spanier , Roger Woods, The impact of data characteristics and hardware topology on hardware selection for low power DSP, Proceedings of the 1998 international symposium on Low power electronics and design, p.94-96, August 10-12, 1998, Monterey, California, United States
	Enrico Macii , Massoud Pedram , Fabio Somenzi, High-level power modeling, estimation, and optimization, Proceedings of the 34th annual conference on Design automation, p.504-511, June 09-13, 1997, Anaheim, California, United States
	R. Kastner , A. Kaplan , S. Ogrenci Memik , E. Bozorgzadeh, Instruction generation for hybrid reconfigurable systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.605-627, October 2002
	William E. Dougherty , David J. Pursley , Donald E. Thomas, Subsetting Behavioral Intellectual Property for Low Power ASIP Design, Journal of VLSI Signal Processing Systems, v.21 n.3, p.209-218, July 1999
	Sanjay Sharma , Sanjay Attri , R. C. Chauhan, Low-power VLSI synthesis of DSP systems, Integration, the VLSI Journal, v.36 n.1-2, p.41-54, September 2003
	Lijun Gao , Keshab K. Parhi, Models for Architectural Power and Power Grid Noise Analysis on Data Bus, Journal of VLSI Signal Processing Systems, v.44 n.1-2, p.25-46, August 2006
	C. A. J. van Eijk , E. T. A. F. Jacobs , B. Mesman , A. H. Timmer, Identification and exploitation of symmetries in DSP algorithms, Proceedings of the conference on Design, automation and test in Europe, p.119-es, January 1999, Munich, Germany