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Register-transfer level estimation techniques for switching activity and power consumption
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Source International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 158 - 165  
Year of Publication: 1997
ISBN:0-8186-7597-7
Authors
Anand Raghunathan  Dept. of EE, Princeton Univ., Princeton, NJ
Sujit Dey  C&CRL, NEC, Princeton, NJ
Niraj K. Jha  Dept. of EE, Princeton Univ., Princeton, NJ
Sponsors
IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
IEEE Computer Society  Washington, DC, USA
Bibliometrics
Downloads (6 Weeks): 10,   Downloads (12 Months): 59,   Citation Count: 23
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ABSTRACT

We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on word-level data, we construct piecewise linear models that capture the variation of output glitching activity and power consumption with various word-level parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, registers, vector logic operators, etc. Since the final implementation of the controller is not available during high-level design iterations, we develop techniques that estimate glitching activity at control signals using control expressions and partial delay information. Experiments on example RTL designs resulted in power estimates that were within 7% of those produced by an inhouse power analysis tool on the final gate-level implementation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E K. Jha and N. D. Dutt, "Rapid estimation for parameterized components in high-level synthesis," IEEE Trans. VLSI Systems, vol. 1, pp. 296-303, Sept. 1993.
 
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S.R. Powell and E M. Chau, "Estimating power dissipation of VLSI signal processing chips: the PFA technique," in Proc. VLSI Signal Processing IV, pp. 250-259,1990.
 
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CSIM Version 5 Users Manual. Systems LSI Division, NEC Corp., 1993.
 
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S. Dey, A. Raghunathan, and N. K. Jha, "Register-trasfer level estimation techniques for switching activity and power consumption," Tech. Rep. 96-C017-4, NEC USA, Princeton, NJ, Apr. 1996.
 
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G. Casella and R. L. Berger, Statistical Inference. Duxbury Press, Belmont, CA, 1990.
 
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High-level synthesis benchmarks, CAD Benchmarking Laboratory, Research Triangle Park, NC.
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CITED BY  23

Collaborative Colleagues:
Anand Raghunathan: colleagues
Sujit Dey: colleagues
Niraj K. Jha: colleagues