| Register-transfer level estimation techniques for switching activity and power consumption |
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International Conference on Computer Aided Design
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Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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San Jose, California, United States
Pages: 158 - 165
Year of Publication: 1997
ISBN:0-8186-7597-7
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 10, Downloads (12 Months): 59, Citation Count: 23
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ABSTRACT
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on word-level data, we construct piecewise linear models that capture the variation of output glitching activity and power consumption with various word-level parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, registers, vector logic operators, etc. Since the final implementation of the controller is not available during high-level design iterations, we develop techniques that estimate glitching activity at control signals using control expressions and partial delay information. Experiments on example RTL designs resulted in power estimates that were within 7% of those produced by an inhouse power analysis tool on the final gate-level implementation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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C. Ramachandran , F. J. Kurdahi , D. D. Gajski , A. C.-H. Wu , V. Chaiyakul, Accurate layout area and delay modeling for system level design, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.355-361, November 1992, Santa Clara, California, United States
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2
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3
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E K. Jha and N. D. Dutt, "Rapid estimation for parameterized components in high-level synthesis," IEEE Trans. VLSI Systems, vol. 1, pp. 296-303, Sept. 1993.
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4
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Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Provably correct high-level timing analysis without path sensitization, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.736-742, November 06-10, 1994, San Jose, California, United States
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5
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S.R. Powell and E M. Chau, "Estimating power dissipation of VLSI signal processing chips: the PFA technique," in Proc. VLSI Signal Processing IV, pp. 250-259,1990.
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7
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Diana Marculescu , Radu Marculescu , Massoud Pedram, Information theoretic measures of energy consumption at register transfer level, Proceedings of the 1995 international symposium on Low power design, p.81-86, April 23-26, 1995, Dana Point, California, United States
[doi> 10.1145/224081.224096]
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8
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9
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10
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CSIM Version 5 Users Manual. Systems LSI Division, NEC Corp., 1993.
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11
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S. Dey, A. Raghunathan, and N. K. Jha, "Register-trasfer level estimation techniques for switching activity and power consumption," Tech. Rep. 96-C017-4, NEC USA, Princeton, NJ, Apr. 1996.
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12
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G. Casella and R. L. Berger, Statistical Inference. Duxbury Press, Belmont, CA, 1990.
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13
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14
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High-level synthesis benchmarks, CAD Benchmarking Laboratory, Research Triangle Park, NC.
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15
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Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Performance analysis and optimization of schedules for conditional and loop-intensive specifications, Proceedings of the 31st annual conference on Design automation, p.491-496, June 06-10, 1994, San Diego, California, United States
[doi> 10.1145/196244.196477]
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CITED BY 23
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K. S. Khouri , G. Lakshminarayana , N. K. Jha, IMPACT: a high-level synthesis system for low power control-flow intensive circuits, Proceedings of the conference on Design, automation and test in Europe, p.848-854, February 23-26, 1998, Le Palais des Congrés de Paris, France
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Jing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou, A power modeling and characterization method for macrocells using structure information, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.502-506, November 09-13, 1997, San Jose, California, United States
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Zhanping Chen , Kaushik Roy , Edwin K. P. Chong, Estimation of power sensitivity in sequential circuits with power macromodeling application, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.468-472, November 08-12, 1998, San Jose, California, United States
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Kamal S. Khouri , Ganesh Lakshminarayana , Niraj K. Jha, Fast high-level power estimation for control-flow intensive design, Proceedings of the 1998 international symposium on Low power electronics and design, p.299-304, August 10-12, 1998, Monterey, California, United States
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A. Bogliolo , L. Benini , B. Riccó , G. De Micheli, Efficient switching activity computation during high-level synthesis of control-dominated designs, Proceedings of the 1999 international symposium on Low power electronics and design, p.127-132, August 16-17, 1999, San Diego, California, United States
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Anand Raghunathan , Sujit Dey , Niraj K. Jha , Kazutoshi Wakabayashi, Power management techniques for control-flow intensive designs, Proceedings of the 34th annual conference on Design automation, p.429-434, June 09-13, 1997, Anaheim, California, United States
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Luca Benini , Alessandro Bogliolo , Enrico Macii , Massimo Poncino , Mihai Surmei, Regression-based RTL power models for controllers, Proceedings of the 10th Great Lakes symposium on VLSI, p.147-152, March 02-04, 2000, Chicago, Illinois, United States
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