Clock-driven performance optimization in interactive behavioral synthesis

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Clock-driven performance optimization in interactive behavioral synthesis

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International Conference on Computer Aided Design archive
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 154 - 157

Year of Publication: 1997

ISBN:0-8186-7597-7

Authors

Hsiao-Ping Juan	Department of Information and Computer Science, University of California, Irvine, CA
Daniel D. Gajski	Department of Information and Computer Science, University of California, Irvine, CA
Viraphol Chaiyakul	Department of Information and Computer Science, University of California, Irvine, CA

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Washington, DC, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 1, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Clock period optimization during resource sharing and assignment, Proceedings of the 31st annual conference on Design automation, p.195-200, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196346]
	2	Raul Camposano , Wayne H. Wolf, High-Level VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1991
	3	D. D. Gajski, and H. -P. Juan, "A Design Methodology for Interactive Behavioral Synthesis," TR#95-25, Dept. of ICS, UC1, 1995.
	4	Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
	5	H. -P. Juan, D. D. Gajski, and V. Chaiyakul, "Clock-Driven Performance Optimization in Interactive Behavioral Synthesis," TR#96-08, Dept. of ICS, UCI, 1996.
	6	S. Parameswaran, P. Jha, and N. Dutt, "Resynthesizing Controllers for Minimum Execution Time," in Proc. of the 2nd ASP-CHDL, 1994.
	7	Donald E. Thomas , Elizabeth D. Lagnese , John A. Nestor , Jayanth V. Rajan , Robert L. Blackburn , Robert A. Walker, Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench, Kluwer Academic Publishers, Norwell, MA, 1989
	8	VLSI Technology Inc., VDP370 1.0 Micron CMOS Datapath Cell Library, 1991.

CITED BY 2

	Sanghun Park , Kiyoung Choi, Performance-driven scheduling with bit-level chaining, Proceedings of the 36th ACM/IEEE conference on Design automation, p.286-291, June 21-25, 1999, New Orleans, Louisiana, United States
	Dongwan Shin , Andreas Gerstlauer , Rainer Dömer , Daniel D. Gajski, An interactive design environment for C-based high-level synthesis of RTL processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.4, p.466-475, April 2008